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Visitor ejhe360
Visitor
983 Views
Registered: ‎05-10-2017

Setting up IRQ_F2P in a managed IP project, NOT block design

Hi all,

I have a project which uses a workflow of tcl scripts and xci files to generate Xilinx IP, with a verilog-only definition of the top level project. I cannot seem to find how to set up the PS to have a vector input on IRQ_F2P. 

 

I have seen MANY solutions here using the "concat" option to generate the IRQ_F2P vector. Just a sampling of the solutions:
 - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Where-is-16-bit-shared-interrupt-port-IRQ-F2P-15-0/m-p/353845

 - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Why-in-my-design-PL-zynq-interrupt-is-IRQ-F2P-0-0-not-IRQ-F2P-15/m-p/717798

 - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-IRQ-F2P-ports-not-resizing-in-IPI/m-p/655574

 

But, I have not yet found a suitable answer for how to set up the vector IRQ using the managed ip project (basically, creating the processing_system_7.xci) without using the block diagram.

 

So far, I have tried generating a PS with a suitable IRQ from the block diagram, and then I manually copied the "BUSIFPARAM_VALUE.IRQ_F2P.PortWidth" and "BUSIFPARAM_VALUE.IRQ_F2P.SENSITIVITY" into my custom .xci, but the generated output still has width = 1 bit.

 

Any suggestions? 

 

Thanks! Best regards,

EJ

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5 Replies
Moderator
Moderator
970 Views
Registered: ‎09-12-2007

Re: Setting up IRQ_F2P in a managed IP project, NOT block design

I wouldn’t recommend using the PS in a managed ip. Not only for the issue you mention here, but you will likely see issues when trying to export to SDK
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Visitor ejhe360
Visitor
965 Views
Registered: ‎05-10-2017

Re: Setting up IRQ_F2P in a managed IP project, NOT block design

Sure-- but, for the purposes of the situation here, I have a system built around a fully functional PS defined by the processing_system7.xci, with a compatible ps7_init.c that's built into a bootable linux image with Openembedded. I'm not currently concerned with the SDK export (it's a lot of clicks, but has been done). Specifically the project I'm looking at is available here: https://github.com/EttusResearch/fpga/tree/rfnoc-devel/usrp3/top/e300 

 

Since I'm just looking to add an additional PL->PS interrupt, I'm not looking to change the full workflow of this particular project. Even if it's tricky, is there an approach to edit the XCI so it generates the correct IRQ vector width??

 

Thanks!

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Visitor ejhe360
Visitor
941 Views
Registered: ‎05-10-2017

Re: Setting up IRQ_F2P in a managed IP project, NOT block design

I was able to successfully edit the port width of the IRQ_F2P line in the processing system, but it's somewhat of a workaround:

 

1. Generate the processing_system7 Xilinx IP outputs and HDL from the xci file

2. Manually locate the <output-directory>/synth/processing_system7_0.v

3. Edit the port interface for IRQ_F2P to [3:0]

4. Edit the C_NUM_F2P_INTR_INPUTS parameter of processing_system7_v5_5_processing_system7.v to be "4"

 

This created an IRQ_F2P port with the correct width (4, in this case). 

 

Examining the source code of processing_system7_v5_5_processing_system7.v, it appears the only HDL difference is that 3 extra bits are consumed from IRQ_F2P instead of being set to 0s.

 

Are there any anticipated errors here? I will follow up with results from a build and test of the IRQ in linux...

 

Thanks,

EJ

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Visitor ejhe360
Visitor
887 Views
Registered: ‎05-10-2017

Re: Setting up IRQ_F2P in a managed IP project, NOT block design

> Are there any anticipated errors here? I will follow up with results from a build and test of the IRQ in linux...

 

In a rather surprising turn of events, it appears that the approach suggested above DOES work, and I was able to instantiate a new AXI_HP line on a new PS interrupt by manually editing the generated processing_system7 verilog file.

 

Here's the relevant sed commands I've committed to version control:

sed -i 's/input wire \[0 : 0\] IRQ_F2P/input wire \[3 : 0\] IRQ_F2P/g'  <location of processing_system7_0.v>

sed -i 's/C_NUM_F2P_INTR_INPUTS(1)/C_NUM_F2P_INTR_INPUTS(4)/g' <location of processing_system7_0.v>

 

I wouldnt necessarily recommend this approach, but it sure beats changing a non-project workflow...

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Contributor
Contributor
351 Views
Registered: ‎04-19-2016

Re: Setting up IRQ_F2P in a managed IP project, NOT block design

You can set the following property on the IP through TCL:

set_property CONFIG.PCW_NUM_F2P_INTR_INPUTS {16} [get_ips processing_system7_0]
I suspect adding:
 
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS">16</spirit:configurableElementValue>
in the .xci file would work too, but I haven't tried that.
 
As an aside, you can get rid of your .xci files and generate your ips in tcl. The following tcl function is handy:
proc ip_settings args {
    foreach ip [get_ips {*}$args] {
        puts "set_property -dict \[ list \\";
        foreach prop [list_property [get_ips $ip] -regexp {^CONFIG\.\w+$}] {
            if {[string toupper [get_property $prop\.value_src [get_ips $ip]]]=="USER"} {
                puts "$prop \{[get_property $prop [get_ips $ip]]\} \\"
            }
        }
        puts "\] \[get_ips $ip\]"
    }
}
After loading that into Vivado, you can run:
ip_settings processing_system7_0
in the tcl console after customising your ip, and it will print out a set_property command that will set all the settings you changed in a new ip. So in your generation scripts you put:
create_ip -name processing_system7 -vendor xilinx.com -library ip -version 5.5 -module_name processing_system7_0
set_property -dict [ list \
***output of ip_settings goes here***
] [get_ips processing_system7_0]
And you have a shorter, more editable and more easily version controlled way of instantiating IP.
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