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Visitor mgamohamed
Registered: ‎05-26-2015

Sharing JTAG between ISim and SDK for Hardware Co simulation

I use PlanAAhead 14.7 to run Hardware co simulation
I have a problem in running ISim simulation with an embedded core. I have found that Xilinx used "Hardware In Loop" technique to enable ISim simulation embeded core on ZYNQ board. This technque enables JTAG connection with ISim simulator with ZYNQ board.
I have figured out how to run this technique, but I still have a problem:
- Isim is working fine, however debugging the C code through SDK is not possible. I think because they are using the same JTAG cable. 
I followed the application note published by Xilinx titled in "Hardware In The Loop (HIL) Simulation for the Zynq-7000 All Programmable SoC". 
1- I defined our board in hwcosim.bsp file like this
'rps-z7000' => {
'Description' => 'RPS-Z7000',
'Vendor' => 'Huins',
'Type' => 'jtag',
'Part' => 'xc7z020-1clg484',
'Clock' => {
'Period' => 5,
'VariablePeriods' => [ 10, 15, 20, 30 ],
'Pin' => 'L18',
'IOStandard' => 'LVCMOS25',
'BoundaryScanPosition' => 2,
2 - First i I run ISim, and I recive the following message:

ISim P.20131013 (signature 0x7708f090)

This is a Full version of ISim.


# run 0ns

at 0 fs: Note: Downloading bitstream, please wait till status is READY.


at 0 fs: Note: Bitstream download is complete. READY for simulation.


Launch Isim


2 - Then I start "Run All" in the ISim simulator


NOTE: the clock used for the part of the code on FPGA is coming form testbench. This clock starts when I click "Run All" on ISim.


3 - I start debug the code on SDK

Here I recive an error message that SDK cannot open JTAG, and a wrong ACK is recieved.


JTAG error message


How can I fix this problem?




Related Zilinx application notes:

Hardware In The Loop (HIL) Simulation for the Zynq-7000 All Programmable SoC


ISim HW Co-Simulation 14.1 Quick Reference


ISim user guide, Chapter 8


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