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Observer @bucky
Observer
568 Views
Registered: ‎11-22-2018

Sharing ZYNQ On-Chip Memory between CPU

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Hi guys,

I'm going to bare-metal developing on a dual-core ZYNQ device used in AMP mode.
The two Cortex-A9 will share the on-chip memory - the 256kB SRAM block - to communicate one each other.
To ensure data update and coherency between processors, the shared on-chip memory will be marked as "Strongly Ordered" on both sides.

I'm not sure about what happens if both CPUs access the same memory location at the same time.
Does memory arbitration is already managed by system interconnect (e.g. CPU0 takes priority) ?

Looking at ZYNQ TRM and XAPP1079 it seems to me that arbitration is already managed but I'm not 100% sure.

Thanks in advance for the support,

Bucky

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1 Solution

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Scholar ericv
Scholar
534 Views
Registered: ‎04-13-2015

Re: Sharing ZYNQ On-Chip Memory between CPU

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@bucky 

don't worry, the system inter-connect deals with contentioin and yes CPU #0 is always the "winner"  One question for you - it sounds like you are setting the cache to strongly ordered with the purpose of making sure the data gets shared.  Do you require that data to land in memory because a DMA or other external device accesses it? If not then keep the OCM as a regular shared memory: the cache, through the SCU, deals with that and you'll llikely get faster accesses/exchanges.

2 Replies
Scholar ericv
Scholar
535 Views
Registered: ‎04-13-2015

Re: Sharing ZYNQ On-Chip Memory between CPU

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@bucky 

don't worry, the system inter-connect deals with contentioin and yes CPU #0 is always the "winner"  One question for you - it sounds like you are setting the cache to strongly ordered with the purpose of making sure the data gets shared.  Do you require that data to land in memory because a DMA or other external device accesses it? If not then keep the OCM as a regular shared memory: the cache, through the SCU, deals with that and you'll llikely get faster accesses/exchanges.

Observer @bucky
Observer
475 Views
Registered: ‎11-22-2018

Re: Sharing ZYNQ On-Chip Memory between CPU

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Hi eric,

thanks for the answer and the hint about strongly ordered marking.
The OCM will be accessed only by the two cores and you are right the coherence is ensured by SCU.

Thanks again,

Bucky

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