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Visitor an_fpga
Visitor
1,568 Views
Registered: ‎05-20-2012

Slave registers burst writing problem

Hello everyone,

 

I'm about to complete my dissertation but I have encountered a problem I can't figure out so i really need your help...

 

I've created a Base System on XPS 13.4 which includes a ppc440, a 128kB BRAM, a ddr2 memmory and an RS232 as basic peripherals. I've also added a core(slave plb v4.6) implementing a row by column multiplier which contains some slave registers . During the CIP wizard , in the slave interface tab i enabled the "burst and cache-line support",i selected 32-bit "native data width" and 64 "write buffer depth". 

 

So, i've already spent several days and nights searching how to implement burst transfers from ppc440 to my core.

 

My core's inputs are slave registers connected to fifos (if that helps). 

 

Should i change anything inside my user logic file, having to do with signals reffering to burst (for example Bus2IP_BE, Bus2IP_Burst, Bus2IP_BurstLength)?

Or should i change anything in my c code in sdk?

 

I'm looking for a simple example of how to implement burst tranfers from ppc440 to ip peripheral!

 

Thanks In advance!

Nick

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