06-26-2017 08:28 AM
I'm using Vivado 2016.4 on Win10-64. I have a custom IP A (salmon) that is a BD of custom IPs B (blue) and C (yellow) as shown below. IP B is embedding a custom (RTL) register file block, 2x AXI VDMAs and 1x AXI DMA. IP C only has a register file. All AXILite ports are merged into a single port using embedded AXI Interconnects.
IP B and C are built from RTL and XCI. IP A is a BD of AXI Interconnect, B and C.
All of this is implementing OK. I can see all 5 memory blocks listed in the top-level BD that is instantiating IP A, but when the hardware handoff file is exported, the VDMA and DMA software drivers are not generated by the SDK BSP.
Once exported to the SDK, the generated BSP (either baremetal or Linux) is NOT including the VDMA and DMA drivers. Instead, all I see is a generic empty driver for the whole A IP. It's like the SDK is expecting me to provide a monolithic driver for the whole IP. But I would MUCH prefer to simply use the Xilinx VDMA and DMA drivers. The register files are just memory mapped and need no driver.
Is there a way to make the IP Package tool include "instructions (ie set properties)" such that the SDK uses the standard Xilinx drivers instead of expecting some IP-specific driver that I really don't want to provide?
11-29-2018 03:17 PM
11-30-2018 04:58 AM
No. When subcore IPs are embeddded into a larger packaged IP, Vivado and the SDK expects a driver for the whole thing. Drivers for the subcore IPs will not be generated.
Although I never tried it, you could possibly build your own driver using the files from the subcore IPs. They are all in $SDK_INSTALL/data/embeddedsw/XilinxProcessorIPLib/drivers
On my side, because I was tight on schedule, I pulled-out all the subcore IP out of my big IP, such than the tool generates the drivers.
Hopefully Xilinx will come up with something some day...
12-04-2018 03:48 PM