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190 Views
Registered: ‎09-26-2019

Strange behavior with Microblaze during AXI access

Hello,

 

I just finished a design for VCU118. I created a design block, with MicroBlaze, 64b, Linux+MMU support, FP, exceptions, MMU. 

On that I added an AXI interconnect, one of the Master ports I made externally connected, I used that to connect from my Block Design Wrapper to my IP through AXI. However, once I wrote the application on the SDK and began to debug on the board, observing on the ILAs, I noticed the system is duplicating my fields. 

So I have my app, that receives an ethernet packet I decode the packet, get the payload, and send to my device:

Snippet:

unsigned long long *axi_master = XPAR_SYSTEM_MB_U_SYSTEM_MB_I_AXI_MASTER_BASEADDR; //0x44A00000

.. got he packet

...

tcp_recved(tpcb, p->len);

...

if(p->len < 102){
memcpy(_buff,p->payload,p->len-2);
}

...

unsigned long long value;

...

value=0;

value = ((unsigned long ) buff[3] << 24 |
(unsigned long)buff[2] << 16 |
(unsigned long)buff[1] << 8 |
(unsigned long)buff[0]);

*((unsigned long long  *)(XPAR_SYSTEM_MB_U_SYSTEM_MB_I_AXI_MASTER_BASEADDR+REG_OFFSET)) = value;

When I print the content of value (%llX) I get the value 0x4123, as expected, once I check the ILA, I see in wdata the following:

wdata[63:0]   000412300004123

 

Neither If I force 0x00000000000004123 it won't work.

 

How do I fix this? Have anyone else ever found this issue before? What have I done wrong?

 

Because my device on the other end is waiting the 0x4123, and the comparator is always mismatching the content

Any insights are welcome since I'm stuck on this to keep going ahead.

Best Regards,

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Xilinx Employee
Xilinx Employee
107 Views
Registered: ‎10-04-2016

Re: Strange behavior with Microblaze during AXI access

Hi @capunderpantsrlz ,

Can you post a block diagram for your system?

Aliasing on the data bus can happen when there is a mismatch on AXI data widths somewhere in the system.

Regards,

Deanna

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96 Views
Registered: ‎09-26-2019

Re: Strange behavior with Microblaze during AXI access

Hello Deanna,

 

Thanks, what happened was, even selecting MicroBlaze 64Bits, the M_AXI_DP port is still 32 bits wide only, you can take the zcu104_ipi example and change it and you will see what I'm talking about:

Screen Shot 2019-11-15 at 11.29.37 AM.pngScreen Shot 2019-11-15 at 11.31.27 AM.png

I can live with a 32bits address space, however I needed 64bits of data space, that was the expected, but I'm limited to 32 bits address and 32b data widths.Screen Shot 2019-11-15 at 11.33.34 AM.png

My whole BD:

 

Screen Shot 2019-11-15 at 11.35.05 AM.png

 

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