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Explorer
Explorer
3,736 Views
Registered: ‎11-21-2013

Synchronization stage of FIFO IP with independent clock

Hi, Dear All,

 

I generated an FIFO with independent clock from the IP catalog, and it has a option of selecting synchronization stage from 2 up to N (N>2). 

 

I am using this FIFO with the same data width, but with different clocks.  From what i understand, this value i should choose for this synchronization stage is related to the differences of clocks. 

So what does it actually mean?

 

for synchronization stage 2, does it mean that after writing data,  you can read the same data after 2 slower clock cycles?

 

Thanks for anyone answering

 

 

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Historian
Historian
3,730 Views
Registered: ‎01-23-2009

Re: Synchronization stage of FIFO IP with independent clock

When a signal is sampled by an asynchronous clock, the flip-flop doing the sampling may go metastable; taking a value that is neither a one nor a zero. When that occurs, it takes a probabilistic amount of time for the metastability to resolve.

 

Using a metastable signal in your logic can cause system failure. So you have to protect your system against the metastable event. This is done by providing "time" in the form of a number of back to back synchronization flip-flops. Even if the first flip-flop goes metastable, by the time the second flip-flop samples the output of that flip-flop, there is a probability that the metastability will have resolved, and hence the output of the second flip-flop will be stable.

 

Depending on clock frequencies, the number of signal changes per second, the structure of the flip-flop and a few other things, the time provided by two back to back flip-flops may not be sufficient to reduce the probability of metastability of the final output to a level that is acceptable for your system. If it isn't sufficient, then you can increase the number of back to back flip-flops to 3 or 4 or even more - all to get the mean time between failures (MTBF) high enough to be acceptable for your system.

 

The consequence of adding metastability flip-flops is that it does increase the latency of the clock crossing. In a FIFO, this means a longer time between the push (wr_en) and the deassertion of empty, as well as between the pop (rd_en) and the deassertion of full. The time of these conditions will be longer than the length of the metastability chain, since there is some additional logic outside the metastability chain as well, but each additional FF will increase the time.

 

Vivado has the ability to analyze the MTBF of synchronization circuits (in UltraScale devices and beyond) using the report_synchronizer_mtbf command. If you annotate the synchronizer activity properly, you can get the MTBF number from the tool and detetmine if 2 or 3 or 4 FFs is sufficient.

 

Since the FIFO is being implemented from an IP core, the tool will manage the application of the ASYNC_REG property to these flip-flops as well as the clock crossing constraints that are required.

 

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