02-11-2020 07:17 AM - edited 02-12-2020 05:34 AM
I have a code which perfectly fine on the psu_cortexa53_0. It is enclosed to this message.
I would like to use this code on the psu_cortexa53_3. I suppose the only difference should be made here:
Each core has 3 TTC, so I thought if I change 0 to 9, everythings should be fine. But it does not work.
Has anyone any idea what I am doing wrong that I don't see it?
02-12-2020 03:27 AM
You are kind of correct for TTC timer ID that is, set from 0 to 11 but you are not suppose to change the ID value to "XPAR_PSU_TTC_0_DEVICE_ID" variable. This variable has fixed ID i.e. "0". Please have a look you SDK/Vitis implimentation file called "xparameters.h". This file will be generated based on you exported design.
Best approch I'd say, please use our exaples provided at the Git hub - https://github.com/Xilinx/embeddedsw/tree/xilinx-v2019.2/XilinxProcessorIPLib/drivers/ttcps
Have a look "xttcps_tapp_example.c" example and will give you some idea about the TTC timer uage.
All the best.
02-12-2020 05:38 AM
I have used exactly the same example that you mentioned. I had also attached it to this thread but it disappeared somehow, so I have attached it again (main.c).
Maybe I have not formulated my question correctly. I can run a TTC example on core 0, no problem at all.
I want to run it this time on core 3, it does not work! The flag that the interrupt handler should set is never set.
Am I missing any configuration?
Thanks a lot
02-13-2020 02:41 AM
02-13-2020 07:37 AM
Thanks a lot for your effort. I can show you better what I mean with the help of your example.
Here is the output I get from ARM Cortex-A53 #0.
Starting four Triple-timer interrupt Example TTC0 - First Triple timer/counter Index= 0 XPAR_PSU_TTC_0_DEVICE_ID= 0 XPS_TTC0_0_INT_ID= 0x44 Index= 1 XPAR_PSU_TTC_1_DEVICE_ID= 1 XPS_TTC0_1_INT_ID= 0x45 Index= 2 XPAR_PSU_TTC_2_DEVICE_ID= 2 XPS_TTC0_2_INT_ID= 0x46 Successfully ran TTC0- First Triple-timer TTC1 - Second Triple timer/counter Index= 0 XPAR_PSU_TTC_3_DEVICE_ID= 3 XPS_TTC1_0_INT_ID= 0x47 Index= 1 XPAR_PSU_TTC_4_DEVICE_ID= 4 XPS_TTC1_1_INT_ID= 0x48 Index= 2 XPAR_PSU_TTC_5_DEVICE_ID= 5 XPS_TTC1_2_INT_ID= 0x49 Successfully ran TTC1- Second Triple-timer TTC2 - Third Triple timer/counter Index= 0 XPAR_PSU_TTC_6_DEVICE_ID= 6 XPS_TTC2_0_INT_ID= 0x4a Index= 1 XPAR_PSU_TTC_7_DEVICE_ID= 7 XPS_TTC2_1_INT_ID= 0x4b Index= 2 XPAR_PSU_TTC_8_DEVICE_ID= 8 XPS_TTC2_2_INT_ID= 0x4c Successfully ran TTC2- Third Triple-timer TTC3 - Fourth Triple timer/counter Index= 0 XPAR_PSU_TTC_9_DEVICE_ID= 9 XPS_TTC3_0_INT_ID= 0x4d Index= 1 XPAR_PSU_TTC_10_DEVICE_ID= 10 XPS_TTC3_1_INT_ID= 0x4e Index= 2 XPAR_PSU_TTC_11_DEVICE_ID= 11 XPS_TTC3_2_INT_ID= 0x4f Successfully ran TTC3- Fourth Triple-time
But if I run the exact same code on ARM Cortex-A53 #3, the output looks like this:
Starting four Triple-timer interrupt Example TTC0 - First Triple timer/counter Index= 0 XPAR_PSU_TTC_0_DEVICE_ID= 0 XPS_TTC0_0_INT_ID= 0x44
See the problem? No interrupt comes on the Core 3. I am using Ultrascale+ ZCU102.
I am working on it for a week and it reaaly drives me crazy... :(
02-13-2020 08:47 AM
May be the Timer 1/2/3 are not set it in Vivado project. Please see my attached BD tcl file and generate the project and used a SDK project with my last source file. Also I've attached BOOT.BIN and check if this works at your end or not?
02-13-2020 09:50 AM
This broght to me two questions:
1. What do you mean to set the Timer 1/2/3? How can I set them? May be I am missing something very fundamental...
2. Why do you have an AXI Timer in your design? I thought with ARM we don't need any timer on the PL!
I thank you one more time.
02-13-2020 01:30 PM
02-14-2020 02:05 AM
Seems like it is activated by default:
I found something funnier. The source code you have provided, works on Core0, Core1 with no problems. But not on Core #2 and Core #3. On cores 2 and 3 waits for interrupt for ever...
02-14-2020 05:16 AM
02-14-2020 05:32 AM - edited 02-14-2020 05:41 AM