Timing problem after booting bare-metal application on MicroZed via SSBL
we are using the MicroZed 7010 Board for our bare-metal application in combination with a user interface (Visual Studio 6) on Windows Embedded. The communication between these two components is working via USB.
The general program works fine while debugging over JTAG and also boots correctly using the FSBL over QSPI or SD Card.
For easier software updates to our system we added a SSBL, so that we can just replace the binary bootimage via our Windows Embedded system. The FSBL is therefore loaded into the OCM and then loads the SSBL into the DDR. After that the SSBL initializes the USB communication and waits for the bootimage. The binary image is sent from the user interface side and after receiving it, the bitstream is written into the PL and the code is loaded into the DDR. At last the SSBL does the handoff (first calling the ps7_post_config function) to the received program.
This process principally works as it should: the USB communication stands, the image is being sent and received respectively and the FPGA is being programmed (FPGA Done LED blue). The user interface program also starts correctly, but we suddenly have a timing problem with our clock. Instead of the actual 4kHz clock the signal now jumps during the 250us cycles.
The clock is generated through an external quartz which is connected to a timing pin from the FPGA. There it is rooted through a clock divider to a GPIO and further via AXI IP to the PS.
It seems that only some part of the handoff or the initialization goes wrong.
We would be very thankful for any ideas on what could be the cause of this.