10-25-2017 01:46 AM
A very warm greetings to all!
I am working on a design in which PL generates packets of data, each is of 128 bits length. These packets are generated at random and I want to store these packets at some place so as to access it later for further processing. I can use PS in a polling mode to look for the data packets, but in doing so few packets are lost by the time I reach and store them using PS. Due to this I want to have some logic in the PL with which the PL can directly store the packets in some memory.
I am using Zedboard, so the options to me are I can store these packets in DDR3 memory. I haven't used DDR3 in PL till now.
My question is how can I store these packets in memory? I also heard of FIFO memories. Which one will be the best to use in my case? Any link or user guide will be very much helpful for me.
Thank you all in advance!
10-25-2017 02:32 AM
What you need is an AXI4 Master, which will be able to write data directly into RAM via the Zynq HP AXI Slave ports.
You have two main ways to go about this. One is to build an AXI4 Stream (which is a very simple interface) and pass that on to an AXI Datamover (or AXI DMA, but the Datamover is easier if you're doing it all from the PL without involving the PS). The Datamover takes an AXI4 Stream and converts that to the necessary AXI4 Master interface for talking to the RAM.
The second approach is to build an IP that just has an AXI Master built-in. This gives you more flexibility, but it's potentially more challenging to write. If you're using Vivado HLS then the problem largely disappears; HLS can do an AXI Master in two lines of code.
10-25-2017 09:24 PM
Thanks a lot for your reply and time!
I have come across so many suggestions. Many of these terms are confusing for a beginner like me. I heard of AXI4 streamer, AXI DMA, AXI CDMA, AXI Datamover, etc. I am unable to find the exact thing I should be working on.
Could you please suggest me some reading material or links which are useful in this perspective?
10-25-2017 09:26 PM