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Explorer
Explorer
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Registered: ‎05-14-2017

Understanding AXI DMA and AXI4-Stream protocol parameters

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Hi all.

I am working with an AXI DMA with S2MM port and I realize that I don't have a very clear idea about some parameters, so I have to ask here for further clarifications. I also took a look at this reply [1] but I still have doubts..

The questions about the AXI DMA and AXI4-Stream protocol are the following:

 

AXI DMA questions.

1) Width of Buffer Length Register: I have read many times the explanation from [1] and from the datasheet but I don't understand to what exactly it refers to. How do I should determine this parameter ?

2) Memory Map Data Width: this seems quiet obvious that refears to the width ((in bits) of the data stored in memory.

3) Stream Data Width: this refears to the data lenght (in bits) of the tdata register.

4) Max Burst Size: this parameters specify the width (in bits) of the chunk of data I can read/write from/to the DMA.

5) Buffer Descriptors (BDs): from the XSDK's AXI DMA example I see that the I can select the number of BDs. But how do I manually determine this parameter ?

I am quiet sure about 2, 3, 4 but if I am wrong I will be happy to read any correction. 

 

AXI4-Stream protocol questions:

6) TLAST signal: The AXI4-Stream Protocol Datasheet specifies that this signal must be asserted to notify the end of packet transfer. Supposing that I interface an AXI4-Stream Master IP to the AXI DMA S2MM size, do the packet size must match with the Max Burst Size of the AXI DMA or any other parameter ?

7) AXI4-Stream Master wait count:

The Custom AXI4-Stream Master IP created by Vivado has defined this parameter:

// Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT    = 32

I looked for an explanation of this parameter into the AXI4-Stream protocol datasheet by ARM but I did not find it. The datasheet (can be downloaded from here) only explains that the handshake between TVALID and TREADY, then a transfer from Master to Slave can happen when both of them are asserted, and TVALID cannot wait for TREADY to be asserted. More precisely:

"A master is not permitted to wait until TREADY is asserted before asserting TVALID. Once
TVALID is asserted it must remain asserted until the handshake occurs."

Is the parameter

C_M_START_COUNT = 32

mandatory for a correct transfer ?

Thank you in advance for your clarifications.

Regards,

simozz

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Scholar jg_bds
Scholar
853 Views
Registered: ‎02-01-2013

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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AXI DMA questions.

1) Width of Buffer Length Register: I have read many times the explanation from [1] and from the datasheet but I don't understand to what exactly it refers to. How do I should determine this parameter ?

     This is a parameter that affects the size of the IP.  There's a maximum buffer size that can be supported (2^26), but specifying a smaller value can lead to a smaller IP.  If you're only supporting 16-kB buffers (max), there's no need to have an IP that can support 64-MB buffers.

2) Memory Map Data Width: this seems quiet obvious that refears to the width ((in bits) of the data stored in memory.

     This value specifies the bit-width of the data pipes on the AXI-MM side of the IP. 

3) Stream Data Width: this refears to the data lenght (in bits) of the tdata register.

     Data width, not length, of the data pipe on the AXI-S side of the IP.

4) Max Burst Size: this parameters specify the width (in bits) of the chunk of data I can read/write from/to the DMA.

     This value determines the maximum burst size of AXI-MM transactions. The value can be any power of 2, from 2 to 256. If you're staying in an AXI-4 world, you can crank it up to 256. If you're planning to send data through an AXI-3 system (like the PS or PSU of a Zynq or Zynq MPSoC), then you should set this value to 16.

5) Buffer Descriptors (BDs): from the XSDK's AXI DMA example I see that the I can select the number of BDs. But how do I manually determine this parameter ?

I am quiet sure about 2, 3, 4 but if I am wrong I will be happy to read any correction. 

     You set this number based on how well the servicer of the Buffer Descriptors (APU or RPU, usually) can keep up with their use. If you have a dedicated RPU that's doing nothing but eyeballing this DMA activity, you can probably get by with 2 or 3 BD's. If, on the other hand, you rely on an app running on an APU under Megalinux, it might be a while before your thread gets around to servicing the BD's, so you'll want more of them to keep the DMA from stalling.

AXI4-Stream protocol questions:

6) TLAST signal: The AXI4-Stream Protocol Datasheet specifies that this signal must be asserted to notify the end of packet transfer. Supposing that I interface an AXI4-Stream Master IP to the AXI DMA S2MM size, do the packet size must match with the Max Burst Size of the AXI DMA or any other parameter ?

     The answer to this depends on a number of configuration and operational settings.

     To some degree, so do the other answers above. You really need determine a particular activity that you want the AXI DMA to perform, then read the manual to see how best to do it.

7) AXI4-Stream Master wait count:

The Custom AXI4-Stream Master IP created by Vivado has defined this parameter:

// Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT    = 32

Is the parameter... mandatory for a correct transfer ?

You need to look at the use of that parameter in the example code of the IP, to see how it's used. It's very specific to the operation of that IP.


-Joe G.

 

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6 Replies
Scholar jg_bds
Scholar
854 Views
Registered: ‎02-01-2013

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

Jump to solution

AXI DMA questions.

1) Width of Buffer Length Register: I have read many times the explanation from [1] and from the datasheet but I don't understand to what exactly it refers to. How do I should determine this parameter ?

     This is a parameter that affects the size of the IP.  There's a maximum buffer size that can be supported (2^26), but specifying a smaller value can lead to a smaller IP.  If you're only supporting 16-kB buffers (max), there's no need to have an IP that can support 64-MB buffers.

2) Memory Map Data Width: this seems quiet obvious that refears to the width ((in bits) of the data stored in memory.

     This value specifies the bit-width of the data pipes on the AXI-MM side of the IP. 

3) Stream Data Width: this refears to the data lenght (in bits) of the tdata register.

     Data width, not length, of the data pipe on the AXI-S side of the IP.

4) Max Burst Size: this parameters specify the width (in bits) of the chunk of data I can read/write from/to the DMA.

     This value determines the maximum burst size of AXI-MM transactions. The value can be any power of 2, from 2 to 256. If you're staying in an AXI-4 world, you can crank it up to 256. If you're planning to send data through an AXI-3 system (like the PS or PSU of a Zynq or Zynq MPSoC), then you should set this value to 16.

5) Buffer Descriptors (BDs): from the XSDK's AXI DMA example I see that the I can select the number of BDs. But how do I manually determine this parameter ?

I am quiet sure about 2, 3, 4 but if I am wrong I will be happy to read any correction. 

     You set this number based on how well the servicer of the Buffer Descriptors (APU or RPU, usually) can keep up with their use. If you have a dedicated RPU that's doing nothing but eyeballing this DMA activity, you can probably get by with 2 or 3 BD's. If, on the other hand, you rely on an app running on an APU under Megalinux, it might be a while before your thread gets around to servicing the BD's, so you'll want more of them to keep the DMA from stalling.

AXI4-Stream protocol questions:

6) TLAST signal: The AXI4-Stream Protocol Datasheet specifies that this signal must be asserted to notify the end of packet transfer. Supposing that I interface an AXI4-Stream Master IP to the AXI DMA S2MM size, do the packet size must match with the Max Burst Size of the AXI DMA or any other parameter ?

     The answer to this depends on a number of configuration and operational settings.

     To some degree, so do the other answers above. You really need determine a particular activity that you want the AXI DMA to perform, then read the manual to see how best to do it.

7) AXI4-Stream Master wait count:

The Custom AXI4-Stream Master IP created by Vivado has defined this parameter:

// Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT    = 32

Is the parameter... mandatory for a correct transfer ?

You need to look at the use of that parameter in the example code of the IP, to see how it's used. It's very specific to the operation of that IP.


-Joe G.

 

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Explorer
Explorer
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Registered: ‎05-14-2017

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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Hello @jg_bds,

First of all thank for your time.

>> This is a parameter that affects the size of the IP.  There's a maximum buffer size that can be supported (2^26), but specifying a smaller value can lead to a smaller IP.  If you're only supporting 16-kB buffers (max), there's no need to have an IP that can support 64-MB buffers.

So if I understand it well, this refers to an intermediate buffer between S_AXIS_S2MM and M_AXIS_S2MM.

>> You set this number based on how well the servicer of the Buffer Descriptors (APU or RPU, usually) can keep up with their use. If you have a dedicated RPU that's doing nothing but eyeballing this DMA activity, you can probably get by with 2 or 3 BD's. If, on the other hand, you rely on an app running on an APU under Megalinux, it might be a while before your thread gets around to servicing the BD's, so you'll want more of them to keep the DMA from stalling.

I am doing many tests with XSDK and the example provided by Xilinx (xaxidma_example_sg_intr.c), and I cannot figure out a secure fixed value for the BD count..

I think I will return on this with a dedicated topic.

Regards,

simozz

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Scholar jg_bds
Scholar
821 Views
Registered: ‎02-01-2013

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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>> This is a parameter that affects the size of the IP.  There's a maximum buffer size that can be supported (2^26), but specifying a smaller value can lead to a smaller IP.  If you're only supporting 16-kB buffers (max), there's no need to have an IP that can support 64-MB buffers.

So if I understand it well, this refers to an intermediate buffer between S_AXIS_S2MM and M_AXIS_S2MM.

This parameter relates to the maximum size of the source and destination buffers that are accessed within the AXI-MM domain. If you're only dealing with 16-kB buffers, you only need 14-bit counters and registers to track position through them. If you have 64-MB buffers, those counters and registers need to be 26 bits.  It's just a means to optimize the size of the IP. 

-Joe G.

 


 

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Explorer
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Registered: ‎05-14-2017

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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Thanks @jg_bds
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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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@jg_bdscan you please check/comment :

4) Max Burst Size: this parameters specify the width (in bits) of the chunk of data I can read/write from/to the DMA.

     This value determines the maximum burst size of AXI-MM transactions. The value can be any power of 2, from 2 to 256. If you're staying in an AXI-4 world, you can crank it up to 256. If you're planning to send data through an AXI-3 system (like the PS or PSU of a Zynq or Zynq MPSoC), then you should set this value to 16.

-> I believe Zynq is AXI-3 based, but Zynq MPSoC is AXI-4 based? See DS891 :

zynq mpsoc AXI4.jpg

So would that mean that Zynq MPSoC allows for burst of 256 bytes?

note: in PG021 I did read 'When using keyhole operation the Max Burst Length should not exceed 16', but that's only for the specific case of 'keyhole operation'.

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Scholar jg_bds
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Registered: ‎02-01-2013

Re: Understanding AXI DMA and AXI4-Stream protocol parameters

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Your assertion that "Zynq MPSoC allows for burst of 256 bytes" is generally correct. Your excerpt from the DS appears to be correct, too--but is is only a vague bullet item in very short list of the features of those interconnects. (The notion of an interface being "AXI4-based"--instead of AXI4-compliant--reminds me of early HD-compatible television sets, which had no HD tuners in them.)

Since most interfaces from the PL to the PSU contain an AFI, however, this passage from the TRM (UG1085) becomes relevant:

2019-03-25_13-55-15.jpg

So a transaction with an AXI4-compatible burst length can be presented to a PL-PS interface, but it will be converted to a series of AXI3-compatible bursts. My original answer tried to incorporate this fact succinctly, without becoming too complicated.

-Joe G.

 

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