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Visitor trax.xavier
Visitor
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Registered: ‎01-03-2018

Understanding PL of Reference design TRD 2017.2

Hello,

 

I'm playing around with the Reference design TRD 2017.2

 

Now, since I'm a bit of a beginner in FPGA programming, I'm having some troubles to understand some of the parts in the block diagram.

For example in 1.png what are the two axi_interconnect_hpm0 and axi_interconnect_hpm1 doing?

They don't seam to b connected to anything else but the SoC.

Same question for interrupts0 and interrupts1 in 2.png where are the interrupts coming from?

It seams to me that some of the wires are not shown how can I easily see the connections I'm missing?

Or am I missing something completely different?

 

Cheers

Trax

1.png
2.png
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1 Reply
Moderator
Moderator
416 Views
Registered: ‎07-31-2012

Re: Understanding PL of Reference design TRD 2017.2

Hi @trax.xavier,

 

axi_interconnect_hpm ports are low latency AXI master ports and these are connected to AXI interconnect.

HP and HPC are high performance ports. For more details refer to Chapter 15 in UG1085, Zynq US+TRM.

 

The pl_ps_irq ports in Zynq US+ processor block is connect to concat IP which just drives interrupt inputs from interrupt sources which is missing here.

You need to connect interrupt generating IP to Concat IP to pl_ps_irq port.

 

Regards

Praveen

 


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