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Visitor dmeads_10
Visitor
244 Views
Registered: ‎07-27-2019

Unspecified I/O standard in AXI GPIO when set to 1 bit width

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Hi all
trying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream.
[DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: io5_tri_o[0], LED4_tri_o[0], LED1_tri_o[0], switch_tri_i[0], and BTN1_tri_i[0].
I don't even have these ports in my axi gpio when I click on it.
here is my block diagram and constraints file:

##switch
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS33 } [get_ports { switch }];

##led4
set_property -dict { PACKAGE_PIN L15    IOSTANDARD LVCMOS33 } [get_ports { LED4 }];

##led1
set_property -dict { PACKAGE_PIN P14    IOSTANDARD LVCMOS33 } [get_ports { LED1 }];

##BTN1
set_property -dict { PACKAGE_PIN D20    IOSTANDARD LVCMOS33 } [get_ports { BTN1 }];

##io5
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { io5  }];

block diagram.JPG

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Scholar jg_bds
Scholar
154 Views
Registered: ‎02-01-2013

Re: Unspecified I/O standard in AXI GPIO when set to 1 bit width

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What you're not telling us (and you might not have noticed yourself) is that Vivado warned you earlier that it was ignoring the set_property constraints you've listed, above--since it couldn't find those ports.

The PACKAGE_PIN property must be attached to a corresponding PORT. A signal port name is not necessarily the INTERFACE name shown in a block diagram. An interface can contain multiple ports; a GPIO interface can contain up to 3 ports: input, output and tristate.

2019-10-14_16-28-35.jpg

You need to adjust your constraints based on the actual port names.

2019-10-14_16-30-50.jpg

The easiest way to assign these is by opening the Synthesized Design, and then using the IO Ports window to select chip-level IO ports and assign their properties. (Select Layout -> IO Planning if the IO Ports window isn't showing when you open the Synthesized Design.)

2019-10-14_16-39-30.jpg

-Joe G. 

2 Replies
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Scholar jg_bds
Scholar
155 Views
Registered: ‎02-01-2013

Re: Unspecified I/O standard in AXI GPIO when set to 1 bit width

Jump to solution

 

What you're not telling us (and you might not have noticed yourself) is that Vivado warned you earlier that it was ignoring the set_property constraints you've listed, above--since it couldn't find those ports.

The PACKAGE_PIN property must be attached to a corresponding PORT. A signal port name is not necessarily the INTERFACE name shown in a block diagram. An interface can contain multiple ports; a GPIO interface can contain up to 3 ports: input, output and tristate.

2019-10-14_16-28-35.jpg

You need to adjust your constraints based on the actual port names.

2019-10-14_16-30-50.jpg

The easiest way to assign these is by opening the Synthesized Design, and then using the IO Ports window to select chip-level IO ports and assign their properties. (Select Layout -> IO Planning if the IO Ports window isn't showing when you open the Synthesized Design.)

2019-10-14_16-39-30.jpg

-Joe G. 

Xilinx Employee
Xilinx Employee
61 Views
Registered: ‎07-12-2018

Re: Unspecified I/O standard in AXI GPIO when set to 1 bit width

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Hi @dmeads_10 

Add below line in the .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run in the bitstream settings.

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

Best Regards
Abhinay PS
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