09-23-2016 04:57 AM
I need support on how to initiate the CRC check for the configuration memory of PL during the FPGA operation phase using PCAP, other than the CRC check which happens during the bootup of zynq. I have gone through UG470 and XAPP1247 but was unable to find relevant information on how to initiate a CRC at designer's point of interest. This would help me check for any bitflips in the FPGA configuration memory because of SEUs for my application.
Please let me know if this is achievable in the first place and has anybody tried to do similar stuff.
09-23-2016 07:34 AM - edited 09-23-2016 07:34 AM
Use the SEM IP. It is tested, and just works. You do have to make the modifications as suggested in the users guide (allow SEM IP to use ICAP).
09-25-2016 09:42 PM
Thanks for the help. But isn't the SEM IP also prone to SEUs since it will reside on the PL fabric of zynq.
09-29-2016 06:58 AM
Yes. But as it is a tiny use of fabric, it is between !e-3 and 1E-4 likely to be affected (10,000 times less likely to be affected by an upset.
And, if hit, there is a heartbeat to tell you if it has stopped working. INIT_b will also pull low when a bad CRC is found.
So, it is easy to create a fail safe system. (We really do know how to do this, the SEM IP core is in its seventh generation).