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Observer sasisaketh
Observer
4,031 Views
Registered: ‎09-23-2016

User initiated CRC check in Zynq using PCAP interface

Hi,

 

I need support on how to initiate the CRC check for the configuration memory of PL during the FPGA operation phase using PCAP, other than the CRC check which happens during the bootup of zynq. I have gone through UG470 and XAPP1247 but was unable to find relevant information on how to initiate a CRC at designer's point of interest. This would help me check for any bitflips in the FPGA configuration memory because of SEUs for my application. 

 

Please let me know if this is achievable in the first place and has anybody tried to do similar stuff.

 

Thanks,

Saketh

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3 Replies
Scholar austin
Scholar
4,013 Views
Registered: ‎02-27-2008

Re: User initiated CRC check in Zynq using PCAP interface

s,

 

Use the SEM IP.  It is tested, and just works.  You do have to make the modifications as suggested in the users guide (allow SEM IP to use ICAP).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer sasisaketh
Observer
3,961 Views
Registered: ‎09-23-2016

Re: User initiated CRC check in Zynq using PCAP interface

Hi Austin,

 

Thanks for the help. But isn't the SEM IP also prone to SEUs since it will reside on the PL fabric of zynq.

 

Thanks, 

Saketh

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Scholar austin
Scholar
3,901 Views
Registered: ‎02-27-2008

Re: User initiated CRC check in Zynq using PCAP interface

s,

 

Yes.  But as it is a tiny use of fabric, it is between !e-3 and 1E-4 likely to be affected (10,000 times less likely to be affected by an upset.

 

And, if hit, there is a heartbeat to tell you if it has stopped working.  INIT_b will also pull low when a bad CRC is found.

 

So, it is easy to create a fail safe system.  (We really do know how to do this, the SEM IP core is in its seventh generation).

Austin Lesea
Principal Engineer
Xilinx San Jose
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