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Participant sjg69
Participant
1,637 Views
Registered: ‎03-29-2012

VDMA multiple buffers

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I have a z-turn board, and they provide a design / SDK project that will output 1080p video - although it bears a striking resemblance to Digilent's  :) . I have managed to build and deploy the design and see a 1080p output on the screen. All well and good.

 

Now I'd like to extend it a bit so there are 2 (maybe 3) framebuffers - so I can draw into one while DMA is sourcing from the other, then flip the DMA to using the one I've just drawn into, and draw into the (now offscreen) original buffer. This isn't going so well.

 

Here's the design that z-turn provide:

 

Screen Shot 2017-12-15 at 07.31.32.png

 

The axi-vdma module was locked as provided (it was for an earlier version of Vivado than I was using) so I couldn't even look at the configuration screen. I could see in the properties that CONFIG->c_num_fstores was set to 1 though, so I set that to 3. I'm not sure what this does (I can't find it in the guide docs) but it *looks* like a limit on the number of framestores :)

 

Setting that and re-synthesizing didn't actually change anything. So I bit the bullet, upgraded the IPs in the design, and re-synthesized/implemented everything. Now I could see the configuration of the VDMA...

 

Screen Shot 2017-12-15 at 07.41.38.png

... and advanced:

 

Screen Shot 2017-12-15 at 07.42.05.png

 

  ... and it all looked good to me. FWIW, the configuration now looks like:

 

 

CLASS	bd_cell
CONFIG.C_SELECT_XPM	0
CONFIG.Component_Name	hdmi_out_axi_vdma_0_0
CONFIG.c_addr_width	32
CONFIG.c_dlytmr_resolution	125
CONFIG.c_dynamic_resolution	1
CONFIG.c_enable_all	0
CONFIG.c_enable_mm2s_buf_empty	0
CONFIG.c_enable_mm2s_delay_counter	1
CONFIG.c_enable_mm2s_frm_counter	1
CONFIG.c_enable_mm2s_frmstr_reg	0
CONFIG.c_enable_mm2s_fsync_out	0
CONFIG.c_enable_mm2s_param_updt	0
CONFIG.c_enable_mm2s_rst_out	0
CONFIG.c_enable_s2mm_buf_full	0
CONFIG.c_enable_s2mm_delay_counter	1
CONFIG.c_enable_s2mm_frm_counter	1
CONFIG.c_enable_s2mm_frmstr_reg	0
CONFIG.c_enable_s2mm_fsync_out	0
CONFIG.c_enable_s2mm_param_updt	0
CONFIG.c_enable_s2mm_rst_out	0
CONFIG.c_enable_s2mm_sts_reg	0
CONFIG.c_enable_tstvec	0
CONFIG.c_enable_vidprmtr_reads	1
CONFIG.c_flush_on_fsync	1
CONFIG.c_include_internal_genlock	1
CONFIG.c_include_mm2s	1
CONFIG.c_include_mm2s_dre	0
CONFIG.c_include_mm2s_sf	0
CONFIG.c_include_s2mm	0
CONFIG.c_include_s2mm_dre	0
CONFIG.c_include_s2mm_sf	1
CONFIG.c_include_sg	0
CONFIG.c_m_axi_mm2s_data_width	64
CONFIG.c_m_axi_s2mm_data_width	64
CONFIG.c_m_axis_mm2s_tdata_width	32
CONFIG.c_mm2s_genlock_mode	0
CONFIG.c_mm2s_genlock_num_masters	1
CONFIG.c_mm2s_genlock_repeat_en	0
CONFIG.c_mm2s_linebuffer_depth	4096
CONFIG.c_mm2s_linebuffer_thresh	4
CONFIG.c_mm2s_max_burst_length	16
CONFIG.c_mm2s_sof_enable	1
CONFIG.c_num_fstores	3
CONFIG.c_prmry_is_aclk_async	1
CONFIG.c_s2mm_genlock_mode	0
CONFIG.c_s2mm_genlock_num_masters	1
CONFIG.c_s2mm_genlock_repeat_en	1
CONFIG.c_s2mm_linebuffer_depth	512
CONFIG.c_s2mm_linebuffer_thresh	4
CONFIG.c_s2mm_max_burst_length	8
CONFIG.c_s2mm_sof_enable	1
CONFIG.c_s_axis_s2mm_tdata_width	32
CONFIG.c_single_interface	0
CONFIG.c_use_fsync	1
CONFIG.c_use_mm2s_fsync	0
CONFIG.c_use_s2mm_fsync	2
LOCATION	4 1310 910
NAME	axi_vdma_0
PATH	/axi_vdma_0
SCREENSIZE	340 140
TYPE	ip
VLNV	xilinx.com:ip:axi_vdma:6.3

 

And I can still set up VDMA with a single framebuffer using the derived BSP from the HDF I get when I export the implemented design to the SDK.

 

... However (finally, the problem :) )

 

I can't get the DMA to change where it's pulling data from. I've attached a zip of the source code I'm using. If I uncomment the line that calls dpyAdvance() - code included below...

 

/******************************************************************************\
|* Enable parking on the current display
\******************************************************************************/
int dpyPark(DpyCtrl *dpy)
	{
	int ok = XAxiVdma_StartParking(dpy->vdma, dpy->curFrame, XAXIVDMA_READ);
	if (ok != XST_SUCCESS)
		{
		printf("Unable to park channel: error %d\n", ok);
		return XST_FAILURE;
		}

	return XST_SUCCESS;
	}
	
/******************************************************************************\
|* Flip the display to the next frame
\******************************************************************************/
void dpyAdvance(DpyCtrl *dpy)
	{
	dpy->curFrame = (dpy->curFrame + 1 ) % _numFrames;
	if (dpy->state == DPY_RUNNING)
		dpyPark(dpy);
	}
	

... I get the message that it was "unable to park channel", with an error code of '1', which is just XST_FAILURE, presumably derived from the call to 'XAxiVdma_ChannelStartParking()'. I also don't get any HDMI output at all as far as I can tell.

 

Ultimately of course, I'd want this to be triggered in an interrupt context on end-of-frame, but for now, the code just triggers it every 0.1 secs.

 

So, any ideas on what I'm doing wrong ?

 

Thanks :)

 

Simon

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Participant sjg69
Participant
2,162 Views
Registered: ‎03-29-2012

Re: VDMA multiple buffers

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... aaaand success! To summarise:

 

1) The design needed to be updated to the latest version of the IP cores

2) The design needed to be customised to have 3 (well, >1) framebuffers specified in the axi vdma configuration

3) The user-configuration design parameter 'CONFIG.c_enable_mm2s_param_updt' needed to be set in the IP properties

4) The s/w needed to set the number of framebuffers available using XAxiVdma_SetFrmStore() once (3) was set.

 

... and then it worked fine. I see the screen alternating between 3 framebuffers @1080p in front of me :) Which is pretty cool, considering it's just the normal output pins of the Zynq that are driving the TDMS.

 

 

 

 

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Participant sjg69
Participant
1,616 Views
Registered: ‎03-29-2012

Re: VDMA multiple buffers

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Update:

 

So, it seems as though the bitstream for the '3' framestore design somehow didn't get passed through to the SDK project. I've fixed that, and I found the call 'XAxiVdma_SetFrmStore' to set the number of frame-stores that VDMA thinks it has to use.  now I see output thus:

 

Booting HDMI test app v0.1a
Initialising SII9022A
Initialising VDMA
Initialising display controller
 - wrote to frame 0
 - wrote to frame 1
 - wrote to frame 2
Starting display controller
Set num buffers failed: 19
Max frames: 3
FAILED to start display
MM2S_VDMACR=	0x00010002
MM2S_VDMASR=	0x00010001
PARK_PTR_REG=	0x00000000
VDMA_VERSION=	0x62000050
Done

... so it looks as though I need to enable the framestore register, because the only return I can see of '19' (which is XST_NO_FEATURE) is from ...

 

int XAxiVdma_SetFrmStore(XAxiVdma *InstancePtr, u8 FrmStoreNum, u16 Direction)
{
	XAxiVdma_Channel *Channel;

	if(FrmStoreNum > InstancePtr->MaxNumFrames) {
		return XST_FAILURE;
	}

	Channel = XAxiVdma_GetChannel(InstancePtr, Direction);

	if (!Channel) {
		return XST_FAILURE;
	}

	if(XAxiVdma_ChannelIsRunning(Channel)) {
		xdbg_printf(XDBG_DEBUG_ERROR, "Cannot set frame store..."
						"channel is running\r\n");
		return XST_FAILURE;
	}

	if (!(Channel->DbgFeatureFlags & XAXIVDMA_ENABLE_DBG_FRMSTORE_REG)) {
		xdbg_printf(XDBG_DEBUG_ERROR,
			"Frame Store Register is disabled\n\r");
		return XST_NO_FEATURE;
	}

	XAxiVdma_WriteReg(Channel->ChanBase, XAXIVDMA_FRMSTORE_OFFSET,
	    FrmStoreNum & XAXIVDMA_FRMSTORE_MASK);

	Channel->NumFrames = FrmStoreNum;

	XAxiVdma_ChannelInit(Channel);

	return XST_SUCCESS;

}

So, back for another round of synthesis => implementation => export HW => rebuild HDF/BSP => recompile app and see if it works this time ...

 

 

 

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Participant sjg69
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2,163 Views
Registered: ‎03-29-2012

Re: VDMA multiple buffers

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... aaaand success! To summarise:

 

1) The design needed to be updated to the latest version of the IP cores

2) The design needed to be customised to have 3 (well, >1) framebuffers specified in the axi vdma configuration

3) The user-configuration design parameter 'CONFIG.c_enable_mm2s_param_updt' needed to be set in the IP properties

4) The s/w needed to set the number of framebuffers available using XAxiVdma_SetFrmStore() once (3) was set.

 

... and then it worked fine. I see the screen alternating between 3 framebuffers @1080p in front of me :) Which is pretty cool, considering it's just the normal output pins of the Zynq that are driving the TDMS.

 

 

 

 

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