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Observer iguaner
Observer
5,526 Views
Registered: ‎07-20-2009

Vivado 2013.2 and SPI

Hello

 

I cant find AXI SPI core in Vivado "Block Design" tool. There is IIC, Quad SPI and many other cores but there is no SPI.

 

Am I missing something or should I create my own SPI implementation?

 

Thanks for help

Ondrej

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5 Replies
Scholar sampatd
Scholar
5,491 Views
Registered: ‎09-05-2011

Re: Vivado 2013.2 and SPI

Hi,

 

This is a known issue. The workaround at the moment is to use AXI QSPI core in Standard Mode.

 

Alternatively,

 

You can refer to page 86 of the following document to include legacy EDK IPs in Vivado:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug939-vivado-designing-with-ip-tutorial.pdf

 

Regards,

 
Observer iguaner
Observer
5,476 Views
Registered: ‎07-20-2009

Re: Vivado 2013.2 and SPI

Hi,

 

thanks for your help. Using QSPI seems to be a good idea. There is only a problem with Xilinx SW libraries - the loop test as well as sending bytes isnt working correctly.

 

I was able to find a workaround by using my own SW library - there seems to be a problem with receiving the last byte in the message.

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Visitor rlucke
Visitor
5,326 Views
Registered: ‎08-21-2013

Re: Vivado 2013.2 and SPI

Hi,

 

I am also trying to get this to work using the quad spi, but it seems to be losing data. When transferring a message of 100 bytes in loopback mode, I am losing 8 bytes with a 16 byte fifo. With a 256 byte fifo, only the last byte is lost.

It seems like it is losing 1 byte each time the fifo becomes empty. 

When using smaller messages (I tried transferring 5 bytes), the last byte is not received.

 

I am using the driver's XSpi_Transfer() function to transfer the data

 

I find that if I step through the code line by line in debug mode, the transfer completes correctly.

 

 

Any ideas? 

 

Ryan

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Observer iguaner
Observer
5,299 Views
Registered: ‎07-20-2009

Re: Vivado 2013.2 and SPI

My trick to receive all bytes is:

 

1.) Fill TX FIFO with data

2.) Enable SPI

3.) Wait to TX empty flag

4.) Wait to SPI Receive FIFO Occupancy Register == bytes send

 

This way you can send only a few bytes (bytes count must be less than FIFO size), but it is OK for my application. The library from Xilinx seems to have bug with receiving last byte - you can experiment with "loopback function" to see this error.

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Newbie ciccychen
Newbie
3,436 Views
Registered: ‎02-10-2015

Re: Vivado 2013.2 and SPI

I guess the xilinx tool have too much bug issus or AXI_SPI IP have bug

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