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Registered: ‎09-10-2018

Vivado 2019.1 | AXI interconnect bug?

Hi,

My design is as follows:

Screenshot from 2020-01-09 12-03-31.png

M_AXI_HPM0_FPD -> 128 bit wide AXI4 interface

I want to translate it to AXI4LITE & cross clock domains with AXI Interconnect IP (AXI_M_0, AXI_M_1 -> 32 bit wide AXI4LITE interface)

AXI_M_0  -> DDR_Clk clock domain (250 MHz)

AXI_M_1 -> Usr_Clk clock domain (312.5 MHz)

For both ports I have specified its settings

AXI_M_0:

Screenshot from 2020-01-09 12-18-21.png
AXI_M_1:

Screenshot from 2020-01-09 12-08-28.png

AXI_M_1 was translated properly. However, the address width does't translate for AXI_M_0. Should be 32 bits instedad of 40  bits (Design was validated without errors)
Note: see highlited ports

Screenshot from 2020-01-09 12-12-09.png

This problem is clearly clock dependant. When both ports are clock from USR_Clk -> the addr width is 32
                                                                 When both ports are clock from DDR_Clk -> the addr width is 40

Is it a bug or am I doing something wrong?

 

Anton 

 

 

 

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Xilinx Employee
Xilinx Employee
98 Views
Registered: ‎01-09-2019

Re: Vivado 2019.1 | AXI interconnect bug?

Hello u6113500@anu.edu.au 

It looks like you are trying to take your DDR clock outside of IPI with an AXI interface, but may I ask why not include the DDR Controller IP within the IPI block design?

If you are using our DDR controller you would want the full AXI MM interface anyway to access DDR.

Otherwise, I believe the IP is taking the address bits from the Master (Zynq PS) which has a 40-bit address space, since there is a difference between the address and data width of your end slave and the originating master.  Either way, if you want to limit the addressable space in memory, the end pin will only have 32 bits to see and therefore the interconnect would not have any reason to change the address width (any transaction being sent to the output pin would need to be 32 or less bits wide, which the master could not send).  An address width conversion would be simply to remove some bits on output so the interconnect has done that by letting the slave control the amount of bits it can handle.

The other master shows a clock converter (due to the change in clock domain) and so has an opportunity within the interconnect to change address widths, but that does not have to happen before leaving the interconnect.

Thanks,
Caleb
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