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Registered: ‎07-12-2019

Vivado 2019.1: How to configure design in order to Export Hardware


The project I'm currently working on uses an ARM Cortex M0 core, on the Nexys DDR 4 board (part xc7a100tcsg324-1).

I've downloaded the Cortex M0 core through ARM's DesignStart which is provided as obfuscated Verilog files (rather than as a block design/IP block).

The instruction memory is intialised within the design as a register array [][] and initialised using a $readmemh("myfile") statement.

I'd like to find a way to change the instruction memory without re-running implementation + synthesis.


My first attempt was to use the updatemem flow, but I've found that my part is not supported:


Another flow that's available is documented here on ARM's DesignStart tutorials:

I'm trying to get this flow to work, but when I select "File->Export->Export Hardware" and launch the SDK as the tutorial suggests, I can't see an address map as shown in the video.


What am I doing incorrectly? Do I need to instantiate my BRAM as IP using the Block Memory Generator rather than generate it implicity through synthesis? I can share details of my project on request.


Any help would be greatly appreciated.


Please watch the earlier videos in this series before following the steps in this one. This is the fourth video in our series of getting started with Cortex-...
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