Vivado Erase Function - How does it work.. Algorithm?
I am trying to figure out how the erase function works in Vivado. I need more information to how this function works and how, specifically, the method erases non-volatile storage. Does this simply turn registers into 0 and 1 randomly? How the data sectors are affected and what is targeted? (ie how much is erased, the ENTIRE storage?).
I also need to validate that the data is actually no longer there.
I'm still learning, feel free to correct/ point me in the right direction.
Re: Vivado Erase Function - How does it work.. Algorithm?
Welcome to the Xilinx Forum!
I assume you are talking about the erase for configuration memory described on page-59 of document, ug908. Most of the time, configuration memory for the FPGA is a separate IC (connected to the FPGA) that is called flash memory – and we often use what is called NOR flash memory. Flash memory parts that can be used with a specific Xilinx FPGA are listed in the appendices of ug908. Many of these flash memory parts are currently in short supply. So, you will often see posts on this forum from people looking for alternatives to the parts listed in ug908.
Vivado gives you the options to erase either all or part of NOR flash. Erasing a storage bit in NOR flash sets the bit to 1. So, checking that NOR flash is erased means checking that each bit is set to 1. This is done by the Vivado “Blank Check” (see page 59 of ug908).
Programming configuration memory consists of changing some of the NOR flash bits from 1 to 0 (ie. programming cannot change a bit from 0 to 1).