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2,401 Views
Registered: ‎11-26-2015

What constrains the bandwidth on the Zynq HP/GP slave interfaces?

Hi,

 

I'm trying to make sense of what truly determines the maximum bandwidth on the AXI HP/GP slave interface. The TRM seems to suggest that each HP slave maxes out at 1,200 MB/s in each direction (Table 22-2 and 22-8) but I don't see where the 150 MHz IF clock figure comes from.

 

If the Memory Interconnect runs off the DDR_2x clock and the DDR controller runs off the DDR_3x clock, shouldn't the IF clock be somehow derived from the DDR PLL frequency?

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3 Replies
Xilinx Employee
Xilinx Employee
2,332 Views
Registered: ‎02-26-2014

Re: What constrains the bandwidth on the Zynq HP/GP slave interfaces?

Hi,

 

I think, this is the bandwidth at the AXI interface itself. And 150 MHz AXI clock that is provided from PL as input to PS.

This clock need not be in synchronous with DDR clock, as there are synchronizers before data enters FIFOs in PS, see Fig 5-1.

 

Regards,

Ravi

Adventurer
Adventurer
2,297 Views
Registered: ‎01-28-2013

Re: What constrains the bandwidth on the Zynq HP/GP slave interfaces?

@jerome.gobuyan

 

The TRM only mentions a relative performance capabilities. That's not the limit.

 

The maximum performance is decided by the AXI interface width (HP has 64-bit) and the maximum clock speed the interface can operate at (I think it's 200MHz or 250MHz). You must also include the latency between bursts while calculating the theoretical bandwidth.

 

It also depends on where you are sending the data the destination controller must be able to read the data at that rate, otherwise it'll The AXI bus can be held the controller during transaction till it can receive further.

 

For practical purpose, you can identify your design's data path and the interconnects involved and calculate a more reasonable value.

 

 

 

 

 

 

 

2,208 Views
Registered: ‎11-26-2015

Re: What constrains the bandwidth on the Zynq HP/GP slave interfaces?

According to the data sheets (e.g. DS187 Table 19) the maximum AXI interface clock is 250 MHz at the PL-PS boundary. I am aware that the FIFOs take care of the clock domain crossing between PL and the PS, but the other side of those FIFOs are driven by DDR_2x according to the Interconnect Block Diagram (UG585 Figure 5.1). The typical values generated for DDR_2x are significantly higher than the 150 MHz examples given elsewhere in the document. In my design it's more like 355 MHz (1066 MHz / 3), so the bottleneck would seem to be at the PL interface (2 GB/s) (not factoring in DDR3 performance).

 

Tracing through the block diagram I can see how 150 MHz would be a valid example in the case of GP interfaces, where the paths go through a 32-to-64 bit up-conversion and through blocks that run off the CPU_2x clock. The up-conversion effectively cuts the 64-bit performance in half, so for a typical CPU_2x = 300 MHz the effective IF clock rate would be 150 MHz.

 

However, I can't see how 150 MHz would even be a valid IF clock example for HP interfaces. The entire 64-bit path past the FIFOs mostly run off the DDR_2x clock. The same goes for the ACP interface, where the intermediate blocks (SCU, Cache Controller) run off the CPU_6x4x clock.

 

In summary, it seems like there is a copy-paste issue with Table 22-2. I would expect typical values for DDR_2x and CPU_6x4x as IF clocks for the HP and ACP interfaces respectively rather than 150 MHz.

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