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Explorer
Explorer
6,400 Views
Registered: ‎11-17-2015

What happened to my AXI_IIC design? Bus stuck at busy.

I am using a simple ZYNQ CPU and teo AXI_IIC slaves. 

Master DES_IIC has a GPO to enable iLA, and a slave SER_IIC is meant to receive. 

Two jumper wires connects four pads outside the ZYNC chip. 

 

The symptom I saw was the bus is stuck with SCL unable to continue. 

 

iic.jpg

 

 

while (1) {
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_RESETR_OFFSET, 0xA);  // soft reset
	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_RESETR_OFFSET, 0xA);  // soft reset

	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DGIER_OFFSET, 0x80000000);
	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_DGIER_OFFSET, 0x80000000);
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_IIER_OFFSET, 0x86);
	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_IIER_OFFSET, 0x28);

	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_ADR_REG_OFFSET, 0x24); // RX addr to 0x01
	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_RFD_REG_OFFSET, 0x00); // RX RX_FIFO_PIRQ Compare Value.
	XIic_WriteReg( SER_IIC_BASE_ADDR, XIIC_CR_REG_OFFSET, 0x1); // RX, Slave, 0, Enable

	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_CR_REG_OFFSET, 0x3); // Reset, CR.Enable
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_CR_REG_OFFSET, 0x1); // CR.Enable

	XIic_WriteReg( DES_IIC_BASE_ADDR, 0x124, 0x0);
	XIic_WriteReg( DES_IIC_BASE_ADDR, 0x124, 0x1);	// Set GPO to enable iLA capture
	XIic_WriteReg( DES_IIC_BASE_ADDR, 0x124, 0x0);

	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x112); // RX Addr
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x55); // TX FIFO

	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_CR_REG_OFFSET, 0xD); // TX, Master, 0, Enable

	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0xAA); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x11); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x22); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x33); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x44); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x55); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x66); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x77); // TX FIFO
	XIic_WriteReg( DES_IIC_BASE_ADDR, XIIC_DTR_REG_OFFSET, 0x88); // TX FIFO

	k=0;
	do {
		tmp = XIic_ReadReg( SER_IIC_BASE_ADDR, XIIC_SR_REG_OFFSET);
		aas = (tmp >> 1) & 0x1;
		srw = (tmp >> 3) & 0x1;
		k++;
	} while (aas == 0 && k < i_max); // As a slave or TO

	xil_printf("\r\naas = %2x, %8x", aas, tmp);

	if (aas == 1) {  // As a slave
		if (srw == 0) {	// Master write to slave
			k=0;
			do {
				rx_fifo_empty = 0;
				tmp = XIic_ReadReg( SER_IIC_BASE_ADDR, XIIC_SR_REG_OFFSET);
				rx_fifo_empty = (tmp >> 6) & 0x1;
				k++;
			} while (rx_fifo_empty == 0 && k < i_max); // As a slave or TO
			tmp = XIic_ReadReg( SER_IIC_BASE_ADDR, XIIC_DRR_REG_OFFSET);
			xil_printf("\r\nReceived %2x", tmp);
		} else { // Master read from slave
		}
	}	
} // While
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1 Reply
Explorer
Explorer
6,367 Views
Registered: ‎11-17-2015

回复: What happened to my AXI_IIC design? Bus stuck at busy.

I solved by adding pullup.
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