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Observer robin2121
Observer
2,116 Views
Registered: ‎07-03-2017

What is the optimized way to read/write to the DDR ?

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Hello,

 

I use the zynq XNLX-XC7Z020-CLG400 device and I have to access to the DDR. I have to write some images in the DDR from my PL design (which transfer the images).

 

According to the architecture of ZYNQ devices (UG585) I have 3 possible ways to do this.

 

1) Connect my PL design (images burst) to AXI_HP M0 or AXI_HP M1 port of the PS and pass through the  DDR Interconnect and the DDR controler

 

2) Connect my PL design to the ACP port of the PS with AXI stream then pass through the Snoop Control Unit (SCU), L2 cache and DDR controler

 

3) Connect my PL design to the general purpose AXI masters and pass through Slave interconnect and central interconnect then DDR controler

 

The architecture diagram is in the attachments

 

My question is :

 

Which way is the most optimized to acces to the DDR ? And what are the differences between those methods ? (baud rate, consumption, latency, efficiency...)

 

Xilinx_zynq_architecture.png
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Scholar hbucher
Scholar
3,387 Views
Registered: ‎03-22-2016

Re: What is the optimized way to read/write to the DDR ?

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Do you have external DDR or you need to write to the PS DDR? 

 

If the later, I would connect your AXI master to the HP slave interface on the PS.  Driving all this data through the ACP will mess up the ARM cores cache lines, potentially blowing up performance of current tasks running on the PS. 

 

The ACP is good for small pokes where you want smooth integration with the ARM processors. The HP is for bulk data - like images. That is my understanding.

 

 

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Scholar hbucher
Scholar
3,388 Views
Registered: ‎03-22-2016

Re: What is the optimized way to read/write to the DDR ?

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Do you have external DDR or you need to write to the PS DDR? 

 

If the later, I would connect your AXI master to the HP slave interface on the PS.  Driving all this data through the ACP will mess up the ARM cores cache lines, potentially blowing up performance of current tasks running on the PS. 

 

The ACP is good for small pokes where you want smooth integration with the ARM processors. The HP is for bulk data - like images. That is my understanding.

 

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
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Observer robin2121
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Registered: ‎07-03-2017

Re: What is the optimized way to read/write to the DDR ?

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Yes my DDR is external and I have heavy images so I think I will pass through HP0 port.

 

Thanks for your answer !

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Scholar hbucher
Scholar
2,071 Views
Registered: ‎03-22-2016

Re: What is the optimized way to read/write to the DDR ?

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DDR has about 4.2 Gb/s bandwidth; each HP port 256 Mb/s and the GP port is 128 Mb/s.  So you see your DDR is 20x faster than any of these ports alone.

 

Conversely, accessing the PS memory through the slave ports will be painfully slow and if you reach out to external DDR through the GP port is even slower. 

 

If your DDR is external to the PS (access through MIG) then you would want to access it directly through a separate AXI interconnect. You get much more bandwidth into the DDR. 

 

xapp1219 has a good wrap on this entire issue. 

https://www.xilinx.com/support/documentation/application_notes/xapp1219-system-performance-modeling.pdf

 

 

 

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ddr.PNG
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