10-11-2019 07:39 AM
In the Zynq-7000 DC and AC Switching Characteristics Data Sheet
Table 20 gives PS_CLK RMS clock jitter tolerance as +-0.5%.
My question is what does this mean? After extensive searching of the internet I cannot find a working definition of this parameter. Most RMS jitter is a standard deviation measurement. This spec gives a percent measurement. The open question is, "A percent of what exactly."
Also how does this relate to common data sheet parameters for oscillators. I can find no oscillator data sheet mentions any jitter spec as a percentage. What numbers are we to use?
10-11-2019 07:48 AM
(I am only making assumptions here, but...)
I presume the percentage is the percentage of the clock period - so a 100MHz clock with 0.5% jitter would have 0.05ns (or 50ps) RMS jitter. That's quite a bit!
Jitter is usually specified in parts per million (ppm). So 0.5% would be 5000ppm.
10-11-2019 07:53 AM
Thank you Avrum, I do appriciate your offer to help and also I very much appriciate your informing us as to the soruce of your data, this is critical to good enginnering.
However your answer must be rejected. You use the phrase "I presume the percentage is the percentage of the clock period". I cannot use a presumption. Hopefully someone has a formal deffinition.
10-11-2019 07:54 AM
Im guessing that Xilinx meen , +- 0.5 percen tof the clock period,
but as you say, all oscilators are specified very differently.
trying another way....
Lookin ghere at a schematic
( you might have to log in to see it )
page 30, has the PS_clk driver as a SIT8103,
which has specified rms period jitter of 4 to 6 ps,
Hope som eone form Xilinx will come on.
10-13-2019 05:45 PM
-for what it’s worth, Table 34 in DS925 (Zynq UltraScale) gives PS clock specifications with standard units:
TRMSJPSCLK = input-RMS-clock-jitter = 3ps max
TPJPSCLK = input-period-jitter(Pk-Pk) = 50ps max.
10-22-2019 06:36 AM
This looks like a documentation problem , not a real part problem,
Im certina it will be elaborated upon in the future by Xilinx.
in th emean time, were all enginertrs, and as such experts at making do with poorly defined informatoin , be it fomr mamangemetn or data sheets.
In this case we have both examples of desings done by Xilinx and others that work , with clock sources on, and we have the clock jittter deifned in other ways in the data sheets,
Till the documentaoint is updated, does not seem like a show stopper nor a risk situatoin t use what has been proved to work.
10-22-2019 06:49 AM
Thank you, Dr John Smith. Interesting reading. However, I am still looking forward to a more detailed reply.
10-22-2019 07:06 AM
I just hope that your design is not held up by your waiting for a documentation update .
In th edoc you refered to , there should be a link to report documentaion probolems direct to the documentatoin team, at the bottom of eahc page I seem to rember,
Click on that , and submit your findings.