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Contributor
Contributor
3,168 Views
Registered: ‎06-12-2008

Where should I put the constraints when instantiating an XPS design in ISE 12.3?

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When instantiating an XPS project in ISE (with a VHDL wrapper that uses the same names for IO-ports), how should I handle the constraints files? If I copy the UCF from my XPS project and add to my ISE project I get a lot of warnings about constraints being overridden. Then, if I try to remove my top-level UCF file some of my IO end up being UNLOCATED.
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Moderator
Moderator
4,022 Views
Registered: ‎08-25-2009

Re: Where should I put the constraints when instantiating an XPS design in ISE 12.3?

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Hi,

 

If your EDK project is a sub-module in ISE, ie.

 

my_top.vhd/.v

  --xps_sub.xmp

  --other logic (vhd or v)

 

you should not be worried about your XPS constraint file in /data directory in XPS project directory. This file will be picked up automatically when you run the implementation in ISE.

"Don't forget to reply, kudo and accept as solution."

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3 Replies
Moderator
Moderator
4,023 Views
Registered: ‎08-25-2009

Re: Where should I put the constraints when instantiating an XPS design in ISE 12.3?

Jump to solution

Hi,

 

If your EDK project is a sub-module in ISE, ie.

 

my_top.vhd/.v

  --xps_sub.xmp

  --other logic (vhd or v)

 

you should not be worried about your XPS constraint file in /data directory in XPS project directory. This file will be picked up automatically when you run the implementation in ISE.

"Don't forget to reply, kudo and accept as solution."

View solution in original post

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Contributor
Contributor
3,151 Views
Registered: ‎06-12-2008

Re: Where should I put the constraints when instantiating an XPS design in ISE 12.3?

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Thank you for the answer and sorry for the late reply.

 

I removed the UCF from my ISE project, cleaned and rebuilt netlist in XPS, then ran implementation from ISE.

 

I still have a problem with an IO constraint not being applied.

In /system/data/system.ucf I have these two lines

NET xib_ipci_0_pagesel_pin<0>           LOC = AC33 |  IOSTANDARD = LVCMOS33;
NET xib_ipci_0_pagesel_pin<1>           LOC = AB33 |  IOSTANDARD = LVCMOS33;

 

They are copied (by ISE/Project navigator ?) to a system.ncf file in my ISE project dir.

However, I get these warnings when I run the implementation from ISE:

 

Place:837 - Partially locked IO Bus is found.
 Following components of the bus are not locked:
     Comp: xib_ipci_0_pagesel_pin<0>

 

Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
     Comp: xib_ipci_0_pagesel_pin<0>   IOSTANDARD = LVCMOS25
     Comp: xib_ipci_0_pagesel_pin<1>   IOSTANDARD = LVCMOS33

 

For some reason the location and IO-standard contraint for pagesel_pin<0> is not applied.

 

Any ideas?

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Contributor
Contributor
3,142 Views
Registered: ‎06-12-2008

Re: Where should I put the constraints when instantiating an XPS design in ISE 12.3?

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I found a solution/workaround:

 

I moved the location & IO standard constraints to a new UCF-file (leaving the rest in system/data/system.ucf) and added it to my ISE project and now my IOs gets constrained correctly.

 

 

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