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Visitor dwjbosman
Visitor
401 Views
Registered: ‎06-17-2018

Write Microblaze BRAM from Zynq

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I have a Zynq 7020 design with an extra Microblaze processor in PL.

The Microblaze is connected with a BRAM in a fairly standard approach:

Microblaze1  DLMB -> Local Memory Bus (LMB) 1.0 -> LMB BRAM Controller -> Port A Block Memory generator : bram_1

Microblaze1  ILMB -> Local Memory Bus (LMB) 1.0 -> LMB BRAM Controller -> Port B Block Memory generator: bram_1

Now I want to write the BRAM from the Zynq Arm core (to upload the microblaze firmware). I could use a AXI BRAM Controller, but there are no free ports left on the dual port BRAM memory bram_1.

I could use separate BRAM's for the instruction space and data space of the Microblaze, but in other posts that's not recommended.

What is the best approach?

 

 

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Xilinx Employee
Xilinx Employee
375 Views
Registered: ‎06-02-2017

回复: Write Microblaze BRAM from Zynq

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Hi @dwjbosman ,

 I have met the similar question which the dual port bram is not suitable for the application. In that case, multiple drivers do not access the bram in the same time, so I designed a simple BRAM driver, which make several bram driver can access the same bram from the same port in the different time. This module is very simple, just mux the input control signal according to enable siganl.

I'm not sure if this solution suitable for your case, just take it as reference.

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Xilinx Employee
Xilinx Employee
376 Views
Registered: ‎06-02-2017

回复: Write Microblaze BRAM from Zynq

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Hi @dwjbosman ,

 I have met the similar question which the dual port bram is not suitable for the application. In that case, multiple drivers do not access the bram in the same time, so I designed a simple BRAM driver, which make several bram driver can access the same bram from the same port in the different time. This module is very simple, just mux the input control signal according to enable siganl.

I'm not sure if this solution suitable for your case, just take it as reference.

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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Visitor dwjbosman
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358 Views
Registered: ‎06-17-2018

回复: Write Microblaze BRAM from Zynq

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Dear Zhiq,

 

Thank you for your reply. I was thinking in this direction as well. In Vivado is there a standard "mux" IP which I can use in the block design? Or is it required to add a custom IP block?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-02-2017

回复: Write Microblaze BRAM from Zynq

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@dwjbosman

As I known, there's no such a standard IP or rtl code. I added a customized rtl module in my case.

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