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Observer goli12
Observer
1,570 Views
Registered: ‎08-07-2017

XAPP1171 writing to ZC706 DDR PCIe endpoint

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Below is a ZC706 PCIe endpoint board design. The design is based on XAPP1171, where I have added the Zynq PS to allow DMA from a host to the endpoint DDR memory, which in this case is the PS DDR3 memory (I believe).

 

On the host system, I have developed the driver which is able to map the BARs. In the end, I am able to write some data to 0x00100000, which I believe is the PS DDR3 memory on the ZC706 endpoint, and retrieve the correct data from that location. 

However, I have implemented some bare metal code to verify the writes to the PS DDR3 memory from the host. Reading from 0x00100000 did not yield the same value I have written from the host to the endpoint. This was done using:

 

Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x00).

 

XPAR_PS7_DDR_0_S_AXI_BASEADDR is set to 0x00100000 in xparameters.h.

 

Am I suppose to see any changes by writing to 0x00100000 from the host to PS DDR3 memory by implementing the above bare metal code? I have attached the board design and address map below, which may prove useful for answering the question.

 

Regards

Andrew

 

board design

address map

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Observer goli12
Observer
2,420 Views
Registered: ‎08-07-2017

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

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Given the lack of feedback on Xilinx forums, I have found that you need to enable the data and instruction cache in the SDK, then disable it after read/write to DDR memory. I'm guessing Xil_In/Out32 reads from these caches and thus it did not see an updated value as the caches were not enabled. An example of the cache code is pasted below.

 

Xil_ICacheEnable();
Xil_DCacheEnable();

 

xil_printf("writing to 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR);
Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x1234); 
xil_printf("read at 0x%x: 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR,Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR));

 

Xil_DCacheDisable();
Xil_ICacheDisable();

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Observer goli12
Observer
2,421 Views
Registered: ‎08-07-2017

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

Jump to solution

Given the lack of feedback on Xilinx forums, I have found that you need to enable the data and instruction cache in the SDK, then disable it after read/write to DDR memory. I'm guessing Xil_In/Out32 reads from these caches and thus it did not see an updated value as the caches were not enabled. An example of the cache code is pasted below.

 

Xil_ICacheEnable();
Xil_DCacheEnable();

 

xil_printf("writing to 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR);
Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x1234); 
xil_printf("read at 0x%x: 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR,Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR));

 

Xil_DCacheDisable();
Xil_ICacheDisable();

Observer goli12
Observer
1,342 Views
Registered: ‎08-07-2017

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

Jump to solution

Given the lack of feedback on Xilinx forums, I have found that you need to enable the data and instruction cache in the SDK, then disable it after read/write to DDR memory. I'm guessing Xil_In/Out32 reads from these caches and thus it did not see an updated value as the caches were not enabled. An example of the cache code is pasted below.

 

Xil_ICacheEnable();
Xil_DCacheEnable();

 

xil_printf("writing to 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR);
Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR,0x1234); 
xil_printf("read at 0x%x: 0x%x\n\r",XPAR_PS7_DDR_0_S_AXI_BASEADDR,Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR));

 

Xil_DCacheDisable();
Xil_ICacheDisable();

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Scholar hbucher
Scholar
1,491 Views
Registered: ‎03-22-2016

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

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@goli12

XilIn/Out is just an inline function that sets the value through a pointer

\data\embeddedsw\lib\bsp\standalone_v6_1\src\common\xil_io.h

static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
	volatile u32 *LocalAddr = (volatile u32 *)Addr;
	*LocalAddr = Value;
}

 The ACP connects straight into the L2 cache, bypassing DRAM.

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Visitor atndech
Visitor
201 Views
Registered: ‎05-23-2019

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

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what was the solution you found for your problem. I face something very similar. I am not able to write into DDR but i can read from DDR.

I did try the enabling and disabling of caches, no luck.

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Visitor atndech
Visitor
161 Views
Registered: ‎05-23-2019

Re: XAPP1171 writing to ZC706 DDR PCIe endpoint

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I guess then this is the reason why enabling and disabling caches did not work. but i havent found a solution yet for this problem. could you please suggest in which direction i should go?
I am trying to implement simple AXI DMA on a Zynq 7z030.
I am first trying the example project provided by xilinx in #AR57562.
https://www.xilinx.com/support/answers/57562.html.
I can transmit data from PS to PL but i cannot seem to receive data from PL to PS.
I have changed the component and memory part in the project to suit my board accordingly

- i created a fsbl project.
- i then changed it to run on JTAG mode from QSPI mode.
- i then created helloworld project and added ps7_post_config.



works : ------AXIS_DATA_FIFO <-- AXI DMA <-- DDR
|
|
does not work: -------------------> AXI DMA --> DDR

The s2mm_introut interrupt seems to set at some rare times and mostly it doesnt.

DMAstatus.png
DMA_intr_HLS.PNG
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