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Registered: ‎05-07-2013

XPS Mailbox FIFO depth

Hi all,


Just a couple of question to clear something out. I am using the Mailbox with a dual microblaze system and I know I can increase the mailbox's FIFO depth from the XPS. I am using the Xilinx C libraries for the mailbox to be able to pass a structure from one processor to the other.


- First of all is the FIFO depth in bits or in bytes?

- If I change the address range (for example from 64K to 128K), what does that change in the mailbox core?

- I am using the C blocking functions to transfer the messages. If a message is bigger than the FIFO depth, will the sender wait for the FIFO to be completely empty or continue sending data serially once the receiver begins reading and part of the FIFO is empty?


Thanks and sorry for the newbie questions.


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