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Observer wadenaka87
Observer
487 Views
Registered: ‎09-20-2017

ZCU102 Memory Test Example Hangs

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Hi,

I've attempted to build the Zynq Ultrascale+ MPSoC example in Vivado utilizing the APU, GPIO (base address 0xA000_0000) and BRAM controller (base address 0xB000_0000) without modification for the ZCU102 board.  I exported the hardware design to Xilinx SDK and created a BSP based off it.  I then created the memory test application and verified that the BRAM controller based address matched the value found in the address editor for the top level block design.

When I execute the test the APU hangs at the first write operation which writes to the base address of the BRAM controller.  This requires me to reset the entire board to allow me to reprogram the bit file.

The BIST passes and I'm able to insert some other IP that I have but I'm stuck at reading/writing using the AXI bus.

Any help or suggestions would be greatly appreciated.

 

Thanks,

 

-Wade

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Observer wadenaka87
Observer
473 Views
Registered: ‎09-20-2017

Re: ZCU102 Memory Test Example Hangs

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I found this post which seems to have solved my issue.  https://forums.xilinx.com/t5/Embedded-Development-Tools/FPGA-register-write-hangs/m-p/490732  I enabled the "PL reset" option in the debug configurations for Xilinx SDK.

View solution in original post

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Observer wadenaka87
Observer
474 Views
Registered: ‎09-20-2017

Re: ZCU102 Memory Test Example Hangs

Jump to solution

I found this post which seems to have solved my issue.  https://forums.xilinx.com/t5/Embedded-Development-Tools/FPGA-register-write-hangs/m-p/490732  I enabled the "PL reset" option in the debug configurations for Xilinx SDK.

View solution in original post

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