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Participant canonind
Participant
851 Views
Registered: ‎05-08-2013

ZCU102: Xil_In32 hangs for IP cores in PL

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Hello,

 

I am working with Vivado 2018.1 and with the ZCU102 board. I am running a C application on the A53 core and the problem is, when I use the Xil_In32 function to read in the registers of my custom IP, the application hangs. I tried this also with Xilinx IP s (AXI_GPIO) in PL and the application also hangs.


However I can use the Xil_In32 function for PS IPs (Ethernet Controller for ex.) without any problem. My run configuration looks like this:

 

RunConfig.png

 

Obviously I need to do some additional step, or is running the bare metal app on A53 wrong?

 

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Participant canonind
Participant
915 Views
Registered: ‎05-08-2013

Re: ZCU102: Xil_In32 hangs for IP cores in PL

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Thanks for the replies. I started the project from scratch and now it works. No idea what went wrong last time.

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Voyager
Voyager
839 Views
Registered: ‎03-28-2016

Re: ZCU102: Xil_In32 hangs for IP cores in PL

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Running bare-metal on an A53 is fine.  I suspect that the PL has not been programmed with the bit stream.  When you try to access the AXI-Lite interface of the PL IPs, the AXI-Lite transfer hangs because there is nothing there to access.

 

Before running the sw application, you need to load the bit file.  In SDK, select "Xilinx" -> "Program FPGA" or press the icon with the red arrow and three green boxes.  In the "Program FPGA" box, select "Program".  Once the bit file is loaded, you can run the sw app as before.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Xilinx Employee
Xilinx Employee
815 Views
Registered: ‎08-02-2011

Re: ZCU102: Xil_In32 hangs for IP cores in PL

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Assuming the bitstream is programmed, as Ted mentioned, this type of behavior happens in a number of scenarios:

- Clocks, clock enables, and resets (make sure you're running PSU_INIT)

- The 'custom IP' is receiving a request but never responds via bresp/rresp

- The 'custom IP' is violating spec

- You're mistakenly trying to access the wrong address when you call XilOut32 resulting in a request to a non-mapped address

- A bresp/rresp error will cause the processor to jump to an exception handler and loop forever (by default) making it look like a 'hang'

 

In any case, I would debug it by putting an ILA on the AXI interface at the peripheral.

www.xilinx.com
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Participant canonind
Participant
916 Views
Registered: ‎05-08-2013

Re: ZCU102: Xil_In32 hangs for IP cores in PL

Jump to solution

Thanks for the replies. I started the project from scratch and now it works. No idea what went wrong last time.

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