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Observer pacalet
Observer
5,499 Views
Registered: ‎05-27-2014

ZCU102: how to access the 4GB of DDR4 from PL?

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I designed a simple foo IP with a AXI master interface with 64 bits data buses / 36 bits address buses. I thought I could use it to access the 4GB of the DDR4 SODIMM of the ZCU102 board in the [32GB..64GB[ address range. Under Vivado 2017.3 I packaged the IP, added it to a block design, added the Zynq UltraScale+ MPSoC and ran connection automation to connect the AXI master of my IP to the S_AXI_HP1_FPD slave of the PS.

 

Vivado automatically inserted an AXI SmartConnect between the two but it also reduced the addresses and data widths to 32 bits. And there is apparently no way to convince it that it is not what I want. As a consequence I cannot access the complete DDR4 from my IP and the address editor shows only a 2GB segment of it in the [0..2GB[ address range.

 

Did somebody already encounter this problem and found a workaround?

 

Thanks.

Renaud Pacalet
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Sorry, my response was specific to accessing 36bit address ranges from the PS to PL. I didn't see the full thread.

 

In your case, you are trying to access 36bit address ranges from PL to PS. In order to allow access for the upper address range, to DDR, enable PS-PL_Configuration->address_fragmentation->High_address.

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This will enable the high address range for DDR and PCIE.

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12 Replies
Scholar hbucher
Scholar
5,483 Views
Registered: ‎03-22-2016

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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@pacalet Yeah that is my pet peeve. You have to enable 64-bit addressing in Vivado HLS. However it seems to me that 64-bit modes are not that well tested. I have raised the issue a couple of times here in the forums and while they seem to acknowledge that there is a problem, nothing has been conveyed to me as far as a resolution for the issue (or if there is any issue for that sake).

 

https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/Trouble-with-m-axi-offset-slave-in-64-bit-address-mode/m-p/789606/highlight/true#M9951

 

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Issue-with-AXI-Stream-Fifo-with-AXI4-full-and-64-bit-mode/m-p/791153/highlight/true#M20466

 

The bottom line is - even though 64 bit mode is activated, it seems that Vivado HLS code itself will trim the higher bits of the address.

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
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Observer pacalet
Observer
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Registered: ‎05-27-2014

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Nice to see I'm not the only one. Note: I am not using HLS, just plain handwritten VHDL. So, after all, your problem may be with IP integrator, not with HLS...
Renaud Pacalet
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Observer pacalet
Observer
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Registered: ‎05-27-2014

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Update: I naively expected that the 2017.3.1 update would solve my issue but no, the behavior is still the same. Is there a enable-64-bits flag somewhere in Vivado IP integrator?

Renaud Pacalet
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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I've successfully done it using an interconnect instead of smartconnect.

Observer pacalet
Observer
5,410 Views
Registered: ‎05-27-2014

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Interesting. Can you please tell me what version of Vivado you are using? I tried what you suggest (use an AXI Interconnect instead of a SmartConnect) but it did not change anything under Vivado 2017.3.1: the address editor still shows only a 4GB address space mapped to the low addresses and I still cannot access the 4GB of DDR4...

Renaud Pacalet
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Participant perencia-wc
Participant
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Registered: ‎10-03-2017

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Any progress with that ? I'm facing the same problem trying to use an AXI DMA to read/store on the upper DDR. The automatically generated axi_smc has the correct address width (36 bits) but i'm unable to see the 4GB on the address editor.

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Observer pacalet
Observer
5,229 Views
Registered: ‎05-27-2014

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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No news on my side. I wish I could access these 4GB from the PL but I still didn't find a solution and got no helpful answer here. @johnmcd answered that using an AXI interconnect instead of a SmartConnect should work but I couldn't reproduce this in Vivado 2017.3.1.

Renaud Pacalet
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Xilinx Employee
Xilinx Employee
6,575 Views
Registered: ‎02-01-2008

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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Sorry, my response was specific to accessing 36bit address ranges from the PS to PL. I didn't see the full thread.

 

In your case, you are trying to access 36bit address ranges from PL to PS. In order to allow access for the upper address range, to DDR, enable PS-PL_Configuration->address_fragmentation->High_address.

1.jpg

 

This will enable the high address range for DDR and PCIE.

2.jpg

Scholar hbucher
Scholar
5,013 Views
Registered: ‎03-22-2016

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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@johnmcd Is this related by any chance? 

https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/Incorrect-HLS-address-handling-with-m-axi-64-and-offset-direct/td-p/792844

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
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Xilinx Employee
Xilinx Employee
3,180 Views
Registered: ‎02-01-2008

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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It looks like two different issues to me. The link you provide is with respect to creating a PL master that can access 4GB of DDR.

 

This thread is about enabling visibility of 4GB of PS DDR to a PL master.

 

In that other thread, it looks like you managed to uncover and fix the HLS to hdl issue. And you have provided your design which I expect will be used to fix the problem in future releases.

 

I've recently started dabbling in HLS and I have found it very helpful to use the VIP core to simulate the generated hdl. You can place the pass-through mode VIP core between your HLS master and the interconnect (referring to your earlier block diag). During synthesis, the VIP becomes wires, but during simulation, you can have the HLS facing slave port act as memory, or you can have the interconnect facing VIP master generate stimulus.

Observer pacalet
Observer
3,108 Views
Registered: ‎05-27-2014

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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@johnmcd Thanks a lot, it seems to work (not tested yet on the board).

Renaud Pacalet
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Adventurer
Adventurer
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Registered: ‎01-08-2018

Re: ZCU102: how to access the 4GB of DDR4 from PL?

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I've put a further question relating to this here...

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/ZCU102-how-to-access-the-4GB-of-DDR4-from-PL-in-Vivado-2018-3/td-p/1019029

The solution put forward in this post doesn't seem to be available in Vivado 2018.3

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