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Visitor
Visitor
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Registered: ‎10-08-2019

ZYNQ Ultrascale+ MPSOC Isolation Issue on DDR_LOW

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Hi there,
We are facing a problem when enabling the isolation feature of ZYNQ MPSOC.
So far, we are using vivado 2019.1 and associated petaLinux build system.Our configuration is as following:
  • DDR_LOW from 0x0000_0000 to 0x7FDF_FFFF is not isolated (read/write) and contains linux
  • DDR_LOW from 0x7FE0_0000 to 0x7FFF_FFFF is isolated (Read/Write) and contains ATF and TSP
Once the system has booted we noticed the first 1-MB from 0x7FE0_0000 is isolated (return a bus ERROR by trying to read at 0x7FE0_0000)
But when reading the last 1-MB from 0x7FF0_0000, the system returns a value (consistent with the TSP) when we expect a bus Error.
-------------------------------------------
We have tried an other time by increasing the isolated memory space with the following configuration:
  • DDR_LOW from 0x0000_0000 to 0x3FFF_FFFF is not isolated (read/write) and contains linux
  • DDR_LOW from 0x4000_0000 to 0x7FFF_FFFF is isolated (read/write) and contains ATF and TSP
Once the system has booted, we noticed bus error as expected from 0x4000_0000 to 0x7FEF_FFFF is isolated (bus ERROR by trying to read).
But the last 1-MB from 0x7FF0_0000 to 0x7FFF_FFFF is accessible.
We would appreciate if anyone from the community has faced such issue and if Xilinx employee can investigate on an unexpected bug?
BR
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Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎10-25-2018

Re: ZYNQ Ultrascale+ MPSOC Isolation Issue on DDR_LOW

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Hello There,

Is expected behaviour, please look at sction DDR Software Self-Refresh in PG201

DDR Software Self-Refresh
DDR Software Self Refresh is a TCL-only parameter (not displayed in the wizard User
Interface).
The default value for this parameter (PSU__DDR_SW_REFRESH_ENABLED) is enabled and
must not be disabled. The presence and state of this parameter reserves the lower DDR
(0x7ff00000 to 0x7fffffff when lower 2GB DDR is enabled) for Xilinx's use only (This memory
is used for APU restart and it is always required to be enabled for the PMU by default).
Please ensure that this reserved area is not accessed by your application.

APU will have access to 0x7ff00000 to 0x7fffffff, on top of your permissions, that is why you are observing last 1-MB from 0x7FF0_0000 to 0x7FFF_FFFF is accessible.

if you are not planning to use APU restart mechinsim associated with PMU you can diable this feature by disabling by using set_property on PSU__DDR_SW_REFRESH_ENABLED parameter.

once this is disabled, you will have to build vivado project and the entire bsp. make sure you understand the APU restart functionality and this change consiuously. 

View solution in original post

2 Replies
Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎10-25-2018

Re: ZYNQ Ultrascale+ MPSOC Isolation Issue on DDR_LOW

Jump to solution

Hello There,

Is expected behaviour, please look at sction DDR Software Self-Refresh in PG201

DDR Software Self-Refresh
DDR Software Self Refresh is a TCL-only parameter (not displayed in the wizard User
Interface).
The default value for this parameter (PSU__DDR_SW_REFRESH_ENABLED) is enabled and
must not be disabled. The presence and state of this parameter reserves the lower DDR
(0x7ff00000 to 0x7fffffff when lower 2GB DDR is enabled) for Xilinx's use only (This memory
is used for APU restart and it is always required to be enabled for the PMU by default).
Please ensure that this reserved area is not accessed by your application.

APU will have access to 0x7ff00000 to 0x7fffffff, on top of your permissions, that is why you are observing last 1-MB from 0x7FF0_0000 to 0x7FFF_FFFF is accessible.

if you are not planning to use APU restart mechinsim associated with PMU you can diable this feature by disabling by using set_property on PSU__DDR_SW_REFRESH_ENABLED parameter.

once this is disabled, you will have to build vivado project and the entire bsp. make sure you understand the APU restart functionality and this change consiuously. 

View solution in original post

Highlighted
Visitor
Visitor
223 Views
Registered: ‎10-08-2019

Re: ZYNQ Ultrascale+ MPSOC Isolation Issue on DDR_LOW

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Hi,
Thank you for your reply!
BR
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