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Observer @bucky
Observer
524 Views
Registered: ‎11-22-2018

ZYNQ VME 16bit accesses

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Hi guys,

we are using  a board equipped with a ZYNQ device interfaced to a VME bus.
In order to use VME, a custom PL peripheral shall be developed.

Our idea is to structure the VME peripheral in the following way
* a set of registers used for peripheral configuration
* a memory area, part of PL peripheral, that triggers VME bus transactions

It shall be possible to access VME peripheral memory area in both 8-bit and 16-bit fashion to even or odd addresses.
This handling is required to trigger the corresponding VME bus transactions.

The core is mapped to AXI bus where other PL peripherals are already memory-mapped.
In ZYNQ Technical Reference Manual is stated that "System peripherals come under strongly ordered and device memory" (cfg paragraph 3.2.4 Memory Ordering) and on that kind of memory areas "Accesses cannot be unaligned".

The reason to mark this system peripheral as strongly order is clear, but I'm not sure to have properly understood the aligned accesses constraints.
Does this constraint means that required VME peripheral memory transactions (8b,16b on even or odd addr) cannot be performed if we map the VME peripheral to AXI bus?
Am I missing something?

If the latter is true does exist a workaround to bypass the problem?

Thanks in advance for your support. Any help greatly appreciated.

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1 Solution

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Observer @bucky
Observer
450 Views
Registered: ‎11-22-2018

Re: ZYNQ VME 16bit accesses

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Hi johnmcd,

thanks for your answer and pointing out also the endianess translation matter.

You well remember about VME, the board is a replacement of an outdated one that uses Motorola 68k processor.

After a bit of test on actual ZYNQ demo board (we finally received it : ) the Strongly Ordered region alignment  is related to the performed access type: 8-bit accesses can be done on even and odd addresses, 16-bit access can be done on even addresses.

That kinds of accesses are exactly what is needed by VME bus, so there should be no problems.

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2 Replies
Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎02-01-2008

Re: ZYNQ VME 16bit accesses

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I suggest you take a look at the amba axi protocol specification available from ARM's website.

It's been a great many years since I've worked with VME but if I recall correctly, it was well suited for old 16bit Motorola processors.

So when you design your VME to AXI bridge, you will need to take into consideration big to little endian conversion, and convert unaligned accesses to aligned.

Observer @bucky
Observer
451 Views
Registered: ‎11-22-2018

Re: ZYNQ VME 16bit accesses

Jump to solution

Hi johnmcd,

thanks for your answer and pointing out also the endianess translation matter.

You well remember about VME, the board is a replacement of an outdated one that uses Motorola 68k processor.

After a bit of test on actual ZYNQ demo board (we finally received it : ) the Strongly Ordered region alignment  is related to the performed access type: 8-bit accesses can be done on even and odd addresses, 16-bit access can be done on even addresses.

That kinds of accesses are exactly what is needed by VME bus, so there should be no problems.

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