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Observer guenselmann
Observer
913 Views
Registered: ‎12-03-2018

Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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Hi all!

 

I am currently working on a design involving a Zedboard Mini-ITX with a Zynq XC7Z100-2FFG900 on it (https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-mini-itx-7z100-sys-g-3074457345635221590/?aka_re=1). The board has 1 GB of DDR3 memory for the PS and 1 GB DDR3 connected to the PL. I am new to Zynq designing and I ran out of things to try to resolve my problem, so I decided to ask here. My final goal is to have a design involving the PL DDR3.

 

To get familiar with the system, I ran the out-of-box demo provided by AVNET on zedboard.org (http://zedboard.org/support/design/2056/17). Booted from the SD-card, connected via SSH and ran some programs. The board seems to work so far.

Then I set up a block design in Vivado 2016.4 (I am kind of stuck with this version) containing only the processing system and executed the "Hello World" program in the SDK via JTAG boot. Works great, I get the UART response!

Now I tried to make a design involving the PL DDR3 by following the tutorial which is included in the board file .zip on http://zedboard.org/support/documentation/2056. I attached a screenshot of the block design. When I try to run "Hello World" on this design the LED indicates that the board was programmed successfully, but I don't get any UART output. So I followed the tutorial again, still no luck.

Eventually I decided to extend my working PS-only design by just the MIG for the PL DDR3 (DL here: https://www.dropbox.com/s/f5em9xua567leqi/minimal_example_ddr3.xpr.zip?dl=0), but with this design I also get no UART output. I used the Vivado board automation features of cause. So, I suspect that I have narrowed down the cause of my problems to the MIG. Remember that the out-of-box-demo worked fine and it includes a MIG, but it was made in Vivado 2013.4.

What am I doing wrong that makes the entire system not work as soon as I add a MIG for the PL DDR3? I have tested some other designs not involving the PL DDR3 and they all worked fine. Example: http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

 

I really appreciate your help because I don't know what else to do.

Best regards!

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Screenshot from 2019-01-21 19-27-56.png
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1 Solution

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Moderator
Moderator
860 Views
Registered: ‎03-19-2014

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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which DDR memory is your test code linked to - PL or PS?   If PL, that memory won't exist until after the FSBL is run and the PL is programmed.

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Observer guenselmann
Observer
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Registered: ‎12-03-2018

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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Some updates as the issue persists:

Today I decided to use an older version of Vivado (2015.3) because that is what the most recent board files provided by AVNET are released for.

I set up a fresh project with a minimal design only including the PS and MIG for the PL DDR3, which you can see in the attached screenshot. Long story short, the system still hangs. I assume it hangs because when I run the "Hello World" sample given in the SDK the FPGA LED says that it has been programmed correctly, but I get no UART output. If I try to run the application again, SDK says that another application is still running and asks if I want to reset the processor.

However, I also ran some other applications with surprising (to me at least) results. The "Memory Tests" given in the SDK pass, but I'm not sure what to make of this. Because I then gave the Zynq-specific "Zynq DRAM tests" a go and there I get a lot of errors. Can anyone help me interpret these results?

Screenshot from 2019-01-22 19-37-26.png
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Screenshot from 2019-01-22 20-41-52.png
Screenshot from 2019-01-22 20-43-42.png
Screenshot from 2019-01-22 20-44-33.png
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Moderator
Moderator
861 Views
Registered: ‎03-19-2014

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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which DDR memory is your test code linked to - PL or PS?   If PL, that memory won't exist until after the FSBL is run and the PL is programmed.

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Observer guenselmann
Observer
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Registered: ‎12-03-2018

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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I did not touch the linker scripts after making the Application Projects because I assumed that the tests would automatically include all memories from the bitstream I exported to the SDK from Vivado. Is this what you mean?

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Moderator
Moderator
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Registered: ‎03-19-2014

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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I'd advise you check them out to see where your code is linked.

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Observer guenselmann
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Registered: ‎12-03-2018

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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Alright, I see that I had no clue what I actually tested before. Is it even possible to test the PL DDR, which is connected via AXI, in this way?

EDIT: Well, I just had a look at the linker script for the "Hello World" program and it was set up to be placed in the PL DDR (MIG) by the SDK. It works now after re-generating the script and pointing it to the PS DDR. I don't understand why the SDK would ever think it was a good idea to default to the MIG, but I guess I'm supposed to be the one thinking here.

Do I have to worry about those errors shown by the memory test earlier?

Screenshot from 2019-01-22 21-34-27.png
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Moderator
Moderator
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Registered: ‎03-19-2014

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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The code is linked to OCM, which is what I would expect for the DDR test.    I would use the SDK debugger to see what is going on and look for the hang your seeing.    Make sure ps7_init is run and the PL is programmed. 

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Observer guenselmann
Observer
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Registered: ‎12-03-2018

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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I accepted your initial response as the solution since it pointed me in the right direction of checking the auto-generated linker scripts - see the edit in my last post.

Do I have to worry about those errors shown during the memory test earlier?

Thanks a lot for your help!

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Moderator
Moderator
684 Views
Registered: ‎03-19-2014

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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The DDR eye tests move the eye and tests data.  As the eye shifts there will be more or less errors in your output.   The idea is to see how sensitive your design is to shifts in the eye.

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Visitor jlipsher
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Registered: ‎12-09-2010

Re: Zedboard Mini-ITX (Zynq XC7Z100) seems to hang when PL RAM (MIG) is used

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Hi folks.  I am running into very similar issues with my test setup.  I can't seem to get the example Memory Tests application to talk to the PL DDR through the MIG at all.  I finally - thanks to your mentioning that the PL DDR doesn't exist until after the FSBL has completed - got the UART feedback that the memory test has begun.  I removed all other AXI peripherals from the AXI bus and removed the other memory spaces from the test so that only the PL DDR was to be tested.  As soon as the PS attempts to access the PL DDR, the program hangs.

Currently, I'm loading the memory test application into ps7_ddr_0, and I've artificially restricted the PL DDR to 128M address space beginning at the start of the PS AXI master's space (0x4000_0000).

Any ideas??

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