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Newbie freakuency
Newbie
1,964 Views
Registered: ‎02-22-2018

ZynQ DRAM fails in test

If I understand it right, the project templates for ZynQs in SDK are from Xilinx? Anyway, I own a Zybo-Z7 board with a 7020 which I have tried both the audio demo project from Digilent with and SDK's memory-test project with. The Audio project never finishes recording, i.e., a DMA S2MM event never happens and I suspect it has to do with the DRAM, that the event never happens since there are no data fetched from the DRAM. Because also, for the memory test I have one ZynQ system/project without any PL just to try the DDR3 and only the UART1 activated, and its output is;

 

Connected to /dev/ttyUSB1 at 115200
--Starting Memory Test Application--

NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated

Testing memory region: ps7_ddr_0

    Memory Controller: ps7_ddr_0

         Base Address: 0x100000 

                 Size: 0x1FF00000 bytes 

          32-bit test: FAILED!

          16-bit test: FAILED!

           8-bit test: FAILED!

Testing memory region: ps7_ram_1

    Memory Controller: ps7_ram_1

         Base Address: 0xFFFF0000 

                 Size: 0xFE00 bytes 

          32-bit test: PASSED!

          16-bit test: PASSED!

           8-bit test: PASSED!

--Memory Test Application Complete--

Are there perhaps any already compiled/synthesized projects that I could try for verification of functionality? The odds for a new Zybo board to have broken DRAMs out of the box is fairly small I think, but I do not know what else to think now. I have no other ideas on how to tackle this problem, since example designs does not even work.

 

Thanks for reading! ;-)

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9 Replies
Xilinx Employee
Xilinx Employee
1,920 Views
Registered: ‎07-30-2007

Re: ZynQ DRAM fails in test

There is an additional Zynq DDR-specific memory test in SDK that may be worth trying. I'd suggest trying the memory test, read, and write eye tests.
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Newbie freakuency
Newbie
1,874 Views
Registered: ‎02-22-2018

Re: ZynQ DRAM fails in test

I did that now but it didn't work out so good. After struggling a long time to install Vivado 2016.4 (days) this is what I get.

How would you interpret these results?

 

Starting Memory Test 's' - Testing 1MB length from address 0x100000...

------------------------------------------------------------------------------------------
TEST                   WORD ERROR   PER-BYTE-LANE ERROR COUNT                       TIME
                       COUNT        [ LANE-0 ]  [ LANE-1 ] [ LANE-2 ] [ LANE-3 ]    (sec)
------------------------------------------------------------------------------------------


Memtest_0 (  0: 0)      10581        [   10033] [    4121] [    2131] [    1001]    0.0188744

Memtest_s (  0: 1)      1706         [    1057] [    1058] [    1638] [    1002]    0.00825754

Memtest_s (  0: 2)      2077         [    1022] [    1874] [    1004] [    1233]    0.00825754

Memtest_s (  0: 3)      1244         [    1002] [    1002] [    1218] [    1006]    0.00707789

Memtest_s (  0: 4)      1236         [    1004] [    1004] [    1224] [    1004]    0.00707789

Memtest_s (  0: 5)      1575         [    1001] [    1255] [    1157] [    1190]    0.00766771

Memtest_s (  0: 6)      1413         [    1002] [    1272] [    1019] [    1016]    0.00766771

Memtest_s (  0: 7)      1138         [    1004] [    1004] [    1126] [    1004]    0.00707789

Memtest_s (  0: 8)      1348         [    1004] [    1004] [    1312] [    1004]    0.00707789

Memtest_p (  0: 9)      1417         [    1163] [    1300] [    1001] [    1123]    0.0159252

Memtest_p (  0:10)      1007         [    1006] [    1001] [    1007] [    1007]    0.0147456



Running Read Eye Measurement now ... 

------------------------------------------------------------------------------------------
TEST                 WORD ERROR   PER-BYTE-LANE ERROR COUNT                      TIME
                     COUNT        [ LANE-0 ] [ LANE-1 ] [ LANE-2 ] [ LANE-3 ]    (sec)
------------------------------------------------------------------------------------------

Test offset  64       3382        [    3011] [    3158] [    3067] [    3132]    0.0471859

Test offset  60       3184        [    3061] [    3133] [    3005] [    3045]    0.0465961

Read Eye Result:
[128 units = 1 bit time (ideal eye width)] 

--------------------------------------------------------
Description        LANE-0    LANE-1    LANE-2    LANE-3    
--------------------------------------------------------
EYE [MIN-MAX]  :  [9999,-9999]  [9999,-9999]  [9999,-9999]  [9999,-9999]  
EYE CENTER     :   0/128         0/128         0/128         0/128    
EYE WIDTH      :   -15623.44%   -15623.44%    -15623.44%    -15623.44%



Running Write Eye Measurement now ... 

    ** read all ddrc regs 

    ** read all ddriob regs 

------------------------------------------------------------------------------------------
TEST                WORD ERROR    PER-BYTE-LANE ERROR COUNT              TIME
                     COUNT        [ LANE-0 ] [ LANE-1 ] [ LANE-2 ] [ LANE-3 ]    (sec)
------------------------------------------------------------------------------------------

Test offset  64       3494        [    3068] [    3210] [    3157] [    3212]    0.0471859


Test offset  60       3134        [    3072] [    3114] [    3007] [    3073]    0.0465961

Write Eye Result:
[128 units = 1 bit time (ideal eye width)] 

--------------------------------------------------------
Description        LANE-0    LANE-1    LANE-2    LANE-3    
--------------------------------------------------------
EYE [MIN-MAX]  :  [9999,-9999]  [9999,-9999]  [9999,-9999]  [9999,-9999]  
EYE CENTER     :   0/128         0/128         0/128         0/128    
EYE WIDTH      :   -15623.44%    -15623.44%    -15623.44%    -15623.44%    
EYE ADJUSTED   :   0             0             0             0         
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Xilinx Employee
Xilinx Employee
1,851 Views
Registered: ‎07-30-2007

Re: ZynQ DRAM fails in test

Well, I'd say that you have two memory tests that are failing. It looks like there is either a problem with the settings, or the physical board itself.
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Newbie freakuency
Newbie
1,823 Views
Registered: ‎02-22-2018

Re: ZynQ DRAM fails in test

Thanks for your replies Dylan. I have not tried changing any settings (yet). For the Digilent example that does not work, I believe I should not have to because it is working fine for other people. I was recommended to try the example with Vivado 2016.4 which it is made in, but that did not help. I am really starting to think that the DRAM is damaged in some way now, I'll mail the company which sold it and see what they say.

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Visitor jnevanko
Visitor
1,538 Views
Registered: ‎06-29-2018

Re: ZynQ DRAM fails in test

I am getting the same DDR failures as you on a Digilent Zybo Z7-20 board using 2017.4.  Any luck with your situation?

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Visitor jnevanko
Visitor
1,529 Views
Registered: ‎06-29-2018

Re: ZynQ DRAM fails in test

I got the basic memory test to work by doing the following:

 

1) Install Vivado 2016.4

2) Download the following project (the demo that ships with the board): https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_bist.zip

3) Run through the demo guide:  https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start

   NOTE:

      a) Follow Vivado sections, not SDK hardware handoff or SDK will not find the hardware handoff properly

      b) On step 4.7, make sure to select the higher-level sdk folder, not the one generated by Vivado

      c) On step 4.8, make sure "Copy projects into workspace" is checked as shown in the screenshot

      d) After loading the FPGA and running the demo program, I confirmed HDMI and UART were working properly

4) In this workspace, create the memory test application project, let it build, and run it.

 

At this point, the entire memory test passed for me, including both the DDR and RAM sections.  Rebooting the board (via on/off switch) and running the memory test without first loading the FPGA still passed all tests.  So, seems to me like an issue within the hardware handoff, not a board issue.  I don't yet know if it is a configuration issue or if "turning off" the programmable logic or not having blocks other than the Zynq PS7 causes issues with DDR.

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Visitor jnevanko
Visitor
1,525 Views
Registered: ‎06-29-2018

Re: ZynQ DRAM fails in test

I took that demo project and hacked it down until it was just the Zynq PS7 block with only the UART 1 enabled, programmable logic disabled and all the same DDR settings as the demo.  The memory test still worked.

 

After that, I saved the configuration of the PS7 block and created a new Vivado project from scratch, added the PS7 block, applied the saved configuration, went through all the steps of generating output files, exporting hardware, opening SDK, creating memory test application, running it and it still worked.

 

Attached is the configuration I applied to the Zynq PS7 block.

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Newbie freakuency
Newbie
1,507 Views
Registered: ‎02-22-2018

Re: ZynQ DRAM fails in test

I returned it, so I cannot try your suggestions, which would be interesting.

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Visitor jnevanko
Visitor
1,485 Views
Registered: ‎06-29-2018

Re: ZynQ DRAM fails in test

Turns out there was a bug in their preset.xml file for the Zybo Z7-20 board:

https://github.com/Digilent/vivado-boards/commit/7ed4cb6efb39f7e5caec1758feb6ab1deaa9ad77

 

That was preventing the board's default settings from getting loaded for the processor.  They actually fixed it Feb 21, 2018.  I made a new project with the updated preset file and the memory test worked just fine.

 

So, if anyone has board files from before Feb 21, 2018, make sure to update them by going through section 3 "Installing Digilent Board Files" again:

https://reference.digilentinc.com/vivado/installing-vivado/start

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