UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer nunu
Observer
2,846 Views
Registered: ‎06-08-2017

Zynq-7000 Dual Ethernet Port

Hello,

to the topic "Dual Port Ethernet" on the Zynq 7000 are different descriptions from different sources, but there were no answers to my case.

At first, here are some general information. 
The system which I work on is:
A custom board based on the Eval-Board zc706 with a xc7z030ffg676-2.
From the hardware view are two Ethernet Ports integrated, one is connected to another device and the second is connected to a switch.


For the software development I use:

Vivado 2016. 2 (64 bit)
SDK, freeRTOS (OS Version 1.1), LWIP141 (Version 1.5)

As starting point I used the original EchoServer code to test the system without DHCP.

With the standard code and single Ethernet port configuration, everything works fine. The ping and EchoServer response works.


My requirements are to use two Ethernet Port simultaneously.
One for communication with another device with a switch in between and one for a FTP connection with a second device with a direct connection.

The startup phase is as follows:
At power on a uboot starts to load the EchoServer application from a TFTP-Server over Eth0 port of the uboot and load the application into the memory.
From this point, only one Ethernet port can activate to the same time.

On the site [1] is described that, the Zynq-7000 AP SoC has an in-built DUAL Giga bit Ethernet controllers which can support 10/100/1000 Mb/s EMAC configurations compatible with the IEEE 802.3-2008 standard.

PIC02.jpg

In this picture is shown 3 possibilities to implement Ethernet-Ports:

1.PS-GEM0 is connected to the Marvell PHY through the reduced gigabit media independent interface (RGMII), which is the default setup
for the ZC706 board.
2.PS Ethernet (GEM1) that is connected to a 1000BASE-X physical interface in PL through an EMIO interface and
3.PL Ethernet implemented as soft logic in PL and connected to the 1000BASE-X physical interface in PL.

To fulfill the requirement I mentioned before the first scenario should be the right solution. 

We don't use Marvell PHY on our board we use a Mircel. Here the autonegotiation capability should be deactived in the LWIP settings. I have set Config_linkspeed1000. I have read that this behavior was fixed, in in later versions.

 

 

In the Vivado project within the properties of the "ZYNQ processing system" are shown in the picture below.
Ethernet 0 (MIO 16-27) and 1 (MIO 28-39) in "ZYNQ processing system" are activ without EMIO.
PIC01.jpg


From this point the HW is export to SDK.
In the file "system.hdf" are shown two entries in the Address Map for the core0


PIC03.jpg

The important Source-Code Parts are, which make the Zynq-7000 platform reachable over the ping command

 
    /*Configuration of port 0*/
	struct netif *netif;
    struct ip_addr ipaddr, netmask, gw;
        /* the mac address of the board. this should be unique per board */
    unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x34 };  
    netif = &server_netif;

    /* initliaze IP addresses  */
    IP4_ADDR(&ipaddr,  192, 168, 100, 101);					
    IP4_ADDR(&netmask, 255, 255, 255,  0);
    IP4_ADDR(&gw,      192, 168, 100, 1);

	
	/* Add network interface to the netif_list, and set it as default */
    //PLATFORM_EMAC_BASEADDR_SWITCH   = XPAR_XEMACPS_1_BASEADDR = 0xE000C000
	if (!xemac_add(netif, &ipaddr, &netmask, &gw, mac_ethernet_address, PLATFORM_EMAC_BASEADDR_SWITCH)) {
        xil_printf("Error adding N/W interface\r\n");
        return;
    }
    /* specify that the network if is up */
    netif_set_up(netif);
	
	
	
	/*Configuration of port 1*/
	struct ip_addr ipaddr1, netmask1, gw1;
    struct netif *netif1;
	/* the mac address of the board. this should be unique per board */
    unsigned char mac_ethernet_address1[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x35 };
	netif1 = &server_netif1;
	/* initliaze IP addresses  */
    IP4_ADDR(&ipaddr1,  192, 168, 10, 150);					
    IP4_ADDR(&netmask1, 255, 255, 255,  0);
    IP4_ADDR(&gw1,      192, 168, 10, 1);
	
   //PLATFORM_EMAC_BASEADDR_MAIN_CPU = XPAR_XEMACPS_0_BASEADDR = 0xE000B000
	if (!xemac_add(netif1, &ipaddr1, &netmask1, &gw1, mac_ethernet_address1, PLATFORM_EMAC_BASEADDR_MAIN_CPU)) {
	        xil_printf("Error adding N/W interface\r\n");
	        return;
	    }
	/* specify that the network if is up */	
    netif_set_up(netif1);




If I run the application and try to ping on "ping 192.168.100.101" everything is fine
but if I ping from the other port "ping 192, 168, 10, 150" I don't get a response
The output of the Terminal is:

PIC04.jpg

The LWIP setting are:

PIC05.jpg


The common question is:

Does two Ethernet Ports works simultaneously with the Zynq-7000 platform?

Does LWIP and freeRTOS fulfill this requirement?

 

Must the uboot be configured before starting the application?

 

What I could try more ?


Thx in advance and a nice weekend



Resources

[1] http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Performance+%E2%80%93+Gigabit+Ethernet+achieving+the+best+performance
[2] http://www.wiki.xilinx.com/Zynq+PL+Ethernet
[3] https://www.xilinx.com/support/documentation/application_notes/xapp1082-zynq-eth.pdf
[4] http://www.wiki.xilinx.com/Standalone+LWIP+library

Tags (2)
0 Kudos
13 Replies
Scholar vanmierlo
Scholar
2,794 Views
Registered: ‎06-10-2008

Re: Zynq-7000 Dual Ethernet Port

Is your switch connected to the PL as in figure 1 or to the MIO pins as the second picture shows?

0 Kudos
Observer nunu
Observer
2,759 Views
Registered: ‎06-08-2017

Re: Zynq-7000 Dual Ethernet Port

The current design is as it shown in the second picture.

 

In [6] is described in Section Gigabit Ethernet Controller 16.1 on  page 484

 

Quote:

" The Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC compatible
with the IEEE 802.3-2008 standard capable of operating in either half or full duplex mode at all three
speeds. The PS is equipped with two Gigabit Ethernet Controllers. Each controller can be configured
independently. To access pins via MIO, each controller uses an RGMII interface (to save pins). Access
to the PL is through the EMIO which provides the GMII interface (to save pins).
"

 

So it is possible to map both Ethernet Controller over MIO->RGMII ?

 

[6]https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

0 Kudos
Visitor bytownbrooks
Visitor
1,404 Views
Registered: ‎06-21-2018

Re: Zynq-7000 Dual Ethernet Port

Hi

Were you able to solve this issue?  Are they sharing the MDIO lines?

Thanks

Jeremy

Observer thammer
Observer
823 Views
Registered: ‎10-09-2018

Re: Zynq-7000 Dual Ethernet Port

Has anyone identified a solution to the poster's question? I find myself in the same situation- albeit with some different versions:

  • SDK 2018.2
  • FreeRTOS 10 v1.1
  • lwip202 v1.1

My FreeRTOS-based project includes the lwip echo server example to prove out the Ethernet PHY/connections for future use. The Digilent ARTY Z7 that we used as our initial prototype only has one Ethernet PHY/connector, so now that I have our first custom board I am trying to bring up the second connector.

I accept that the lwip echo server example code is simplistic and cannot work with both PHYs at the same time, but I would expect that I can at least "enable" the second PHY.

Pretty much exactly the same setup as the original poster. I realized after an initial test that my first failure was that the MDIO lines had been "disconnected" in the Vivado project- however, I can only connect one PHY at a time:

Enet-MDIO-conflict.png

If I connect the MDIO pins first to one of the controllers (e.g. Ethernet 0) and test, and then connect the MDIO pins to the other controller, I am able to run the LWIP Echo Server and prove the hardware works. But I need to have both available simultaneously. I first thought the hardware designers could just connect the second ethernet device MDIO lines to a different pair of pins but they pointed me to Table  2-4 in the Zynq-7000 SoC TRM which shows the MDIO connection is only available on pins 52 & 53 (MIO package bank 501).

How do I get both Ethernet 0 and Ethernet 1 running with a single MDIO connection?

Thanks!
.Tim

0 Kudos
Highlighted
Visitor bytownbrooks
Visitor
811 Views
Registered: ‎06-21-2018

Re: Zynq-7000 Dual Ethernet Port

Hi

So I was able to solve this issue for my particular configuration.  As you have seen, you can only have the one MDIO interface enabled for either Ethernet 0 or Ethernet 1 at a time.  That being said, this one interface (pins 52 and 53) should be wired to the MDIO interface on both of your PHYs.  Not sure what type of PHYs you are using however they should have configurable MDIO address pins via hardware.  (In my case I was using Marvell devices with ETH0 PHY tied to address 0 and ETH1 PHY tied to address 1).  This will then allow you to address each PHY individually using your shared MDIO connection. 

Now the issue I was experiencing with this setup was that the QNX network driver would always assume that the MDIO interface would be at an offset from the start of base address for the MAC (ie 0xE000B000 for EMAC0 and 0xE000C000 for EMAC1).  If you use the default driver, you could never enable PHY1 connected to EMAC1 because the MDIO interface was not enabled for PHY1.  What I needed to do was modify the driver so that whenever an MDIO access was performed, it would do that access based on an offset from EMAC0 (assuming you enabled the MDIO on Ethernet0 in Vivado), and would set the PHYID properly in the access so it would talk to PHY0 or PHY1 based on their MDIO (MII) address.  So any MDIO access would use ETH0 base address plus the MDIO offset and the data would include the PHY address of either PHY0 or PHY1 depending on which PHY I was configuring.  All other, non MDIO reads and writes would then just be performed at an offset of either EMAC0 or EMAC1 depending on which Ethernet interface you wanted to access.

I havent looked at the LWIP server however if you look at the DetectPhy and Phy read and write routines for the LWIP server you are using, you might find that they are always using the base address of the EMAC you are trying to write to.  You should try to modify them so that the routines always use EMAC0 base address with the proper PHY address  when writing to the PHY. You might find that that will allow you to access the proper PHYs, enable them and then the both Ethernet interfaces will work.   

Observer thammer
Observer
746 Views
Registered: ‎10-09-2018

Re: Zynq-7000 Dual Ethernet Port

@bytownbrooks - Thanks for the response. I do believe that you have identified the basic issue that I am running into.

I have now learned that both PHYs can be enabled and are "running", but actually setting up the links and "talking" on both PHYs is proving to be a challenge.

The lwIP implementation is a Xilinx port and runs on top of the xemacps implementation. To the best of my ability so far, I do not see how it can support a second network interface. If I just enable both, but do not connect a cable to PHY 0, then the output shows PHY 1 autonegotiation completing, but no DHCP IP address obtained because it is doing that on PHY 0!

If I enable both and have cables on both, then it works.

If I change the code to try and add PHY 1 as the interface, it cannot read the ID & speed (status) registers because of the MDIO issue you describe.

If I modify the code to use the PHY 0 address to read the ID & speed (status) registers, then it seems to fail reading the DMA control register. I have not found confirmation, but I surmise that the DMA control register may be something other than MDIO?
The simplest way to change what base address the reads and writes use is to replace it in the XEmacPs_In32 and XEmacPs_Out32 macros. The proper way will be to review all 50+ reads and ?? writes (did not count yet) and modify the base address passed in for those that are MDIO calls and leave it unchanged for the others. Even that will be a bit kludgey as it will require knowing which of the PS Emac devices has the MDIO registers...

I am hoping someone with more experience in the PS Emac support can help me determine if this is a feasible approach or not.

.Tim

0 Kudos
Observer thammer
Observer
670 Views
Registered: ‎10-09-2018

Re: Zynq-7000 Dual Ethernet Port

[PING]

At this point, I have identified the following options for dealing with this issue:

  1. Modify the Xilinx code that ends up in the BSP (lwip202_v1_1/src/contrib/ports/xilinx/) to handle the shared MDIO lines as @bytownbrooks did/suggets
    large cost/effort - high risk
  2. Switch to an alternative TCP stack (FreeRTOS+TCP?) and hope that the Xilinx support code does not have the same limitation
    medium cost/effort - high risk
  3. Re-wire the board to provide separate MDIO lines for each Ethernet controller- we have plenty of unused pins on MIO bank 501- assumes that MDIO can run on pins other than 52 & 53 (as indicated by Table 2-4 in the Zynq-7000 TRM)
    low cost/effort - ?? risk

Guidance would be greatly appreciated.

.Tim

0 Kudos
Observer adnan86
Observer
620 Views
Registered: ‎05-28-2019

Re: Zynq-7000 Dual Ethernet Port

Hi,

I just start to work with Ethernet. My board is also zc706.

I'm looking for several practical examples to learn how to work with Ethernet in my board. Could you please introduce some example that explains how to work with it step by step. or even some example with include all files (hw+sw).

Thanks

0 Kudos
Newbie uecasm
Newbie
512 Views
Registered: ‎10-25-2017

Re: Zynq-7000 Dual Ethernet Port

FWIW, what I did was to wire the MDIO bus only to the first axi_ethernetlite instance and not the second. Then I wrote a "multi mdio" library that knew how to route MDIO access through the first MAC using the correct address bits, and patched lwip to use it.
Observer thammer
Observer
499 Views
Registered: ‎10-09-2018

Re: Zynq-7000 Dual Ethernet Port

@uecasm -

Thank you for the response and suggestion. Sounds like a similar approach to @bytownbrooks solution. Looking more and more like I need to dig into the Xilinx and lwIP code...

0 Kudos
Newbie uecasm
Newbie
476 Views
Registered: ‎10-25-2017

Re: Zynq-7000 Dual Ethernet Port

I don't mind sharing my solution.  Although you probably won't be able to use it directly -- it's against lwIP 1.4.0 and SDK 14.7 for Microblaze, and for a custom board.

The attached is the library package which modifies the lwIP sources and adds the MultiMdio interface.  I don't have the changes in the form of a patch, although I might be able to generate one if it's too hard to work out the changes from the full files.

Initialisation code for it went like this:

// ---------------------------------------------------------------------------
static XEmacLite mdio_emac;
static MultiMdio mdio;

// ---------------------------------------------------------------------------
static void init_mdio(void)
{
	XEmacLite_Initialize(&mdio_emac, XPAR_AXI_ETHERNETLITE_0_DEVICE_ID);
	MultiMdio_Initialize(&mdio, &mdio_emac);
	MultiMdio_Add(&mdio, XPAR_AXI_ETHERNETLITE_0_BASEADDR, 0x10);
	MultiMdio_Add(&mdio, XPAR_AXI_ETHERNETLITE_1_BASEADDR, 0x11);
	MultiMdio_SetGlobalInstance(&mdio);
}

 

0 Kudos
Observer thammer
Observer
392 Views
Registered: ‎10-09-2018

Re: Zynq-7000 Dual Ethernet Port

Do you recall which Vivado Design Suite you were using with this code? 2014.x? x = {1|2|3|4}
Or some other year?
Thanks!
0 Kudos
Newbie uecasm
Newbie
357 Views
Registered: ‎10-25-2017

Re: Zynq-7000 Dual Ethernet Port

It wasn't Vivado at all, it was ISE.  As I said, it was version 14.7.

0 Kudos