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Contributor
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Registered: ‎02-24-2014

Zynq 7z030 FSBL won't configure PL

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Hi all

 

I am having trouble getting the FSBL to configure the PL while booting from QSPI flash, specifically the bootloader times out waiting for the DONE signal.

 

Vivado 2015.2

SDK 2015.2

Custom hardware with Zynq 7030

 

The output on the serial terminal (see below) shows the the bitstream partition is found and is valid, the image is transfered to DDR (I also visually checked its presence via the SDK debugger). The INIT_B line pulses low to show the PL is erased and then stays high - i.e. no errors. The DONE line has an external pull-up and the PUDC is disabled (held high). If I program the FPGA from Vivado at this point, the FSBL unblocks and continues to look for the handover images (not shown here).

 

Xilinx First Stage Boot Loader
Release 2015.2 Aug 10 2015-08:45:17
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x20 0xBB 0x19
MICRON 256M Bits
QSPI is in single flash connection
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 2
Partition Number: 1
Header Dump
Image Word Len: 0x0016CFC8
Data Word Len: 0x0016CFC8
Partition Word Len:0x0016CFC8
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000055D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFBB3866
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00001A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x0016CFC8
PCAP DMA DEST LEN 0xF8007024: 0x0016CFC8
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !
...................................................................................................PCAP transfer timed out
PCAP_FPGA_DONE_FAIL
PCAP Bitstream Download Failed
PARTITION_MOVE_FAIL
▒SBL Status = 0xA00B

 

While in the polling state, I connected Vivado to check the status registers. I've attached the output report including my notes.

Curiously, I see following; this would seem to be triggering the other errors.

 

BIT07_GHIGH_STATUS 0 "0" - The device does not receive the entire configuration data stream. 

 

From the boot loader output, the lengths would seem to be correct for a 7030 bitstream.

 

I repeated the process of creating an FSBL, creating a BIN and booting from QSPI on my Zedboard (7020). This worked correctly, showing the following:

...
PCAP STATUS 0xF8007014: 0x00000A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0
PCAP DMA DEST LEN 0xF8007024: 0x000F6EC0
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x00000000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x00000000
DMA Done ! FPGA Done ! In FsblHookAfterBitstreamDload function ...

So I believe my steps to be correcty.

 

The three pontential areas I can think of are:

  1. PS configuration in Vivado
  2. Hardware pin configuration
  3. DMA handling larger bitstream of 7030

I've checked all of these as far as I can but now am scratching my head as to what to look for.

 

This answer mentions the StartupClk:JtagClk but I can't find if/how that is used in Vivado.

Any ideas or pointers would be appreciated.

 

Thanks

Chris

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Contributor
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20,879 Views
Registered: ‎02-24-2014

Re: Zynq 7z030 FSBL won't configure PL

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After various investigations, this turned out to be a HW DDR issue after all.

Even thought the Xilinx DRAM tests passed, by default they run with data caching enabled. This was masking DDR access problems. Once we turned off caching in the test tool menu, real errors were observed.

 

Following a fix to the DDR interface, PL configuration from flash worked straight away.

 

 

Chris

 

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Community Manager
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Registered: ‎07-23-2012

Re: Zynq 7z030 FSBL won't configure PL

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To edit the startupclk properties, open the implemented design and select Tools-> Edit device Properties.

 

Under Startup section, you will find startupclk options which you can set to CCLK as shown in below figure.

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Contributor
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Registered: ‎02-24-2014

Re: Zynq 7z030 FSBL won't configure PL

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Thanks for the pointer to the startup clock settings. I wouldn't have found that :)

 

My settings were as default which is the CCLK. For good measure, I regenerated with that and the JTAG clock option but both flash images showed the same failure (as above). Incidently, I also tried the UserClock setting but this failed to generate since I have no other clock input specified.

 

I would expect a failure from the JTAG clock setting since I am running in QSPI boot mode. I assume the CCLK is automatically derived from the main PS clock? This is a 40MHz osc in our case.

 

Thanks

Chris

 

 

 

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Contributor
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Registered: ‎02-24-2014

Re: Zynq 7z030 FSBL won't configure PL

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From other reading, I believe the BIT file needs to be bit-reveresed to work with the Linux xdevcfg driver but that this is not the case for the FSBL. Hopefully, I've got that right.

 

 

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Community Manager
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Registered: ‎07-23-2012

Re: Zynq 7z030 FSBL won't configure PL

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For FSBL the bit file need not be bit-reversed. Are you able to configure the PL section from either from SDK or Vivado HW manager using the .bit file?

From the FSBL log, it looks to me that the partition with bit file was moved successfully to DDR. But for some unknown reason the bitstream data was not transferred to the PL.
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Re: Zynq 7z030 FSBL won't configure PL

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I can configure the PL with the bit file from both Vivado and SDK.

I'm currently examining the DDR contents to see if there is any error following the transfer from flash.

 

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Re: Zynq 7z030 FSBL won't configure PL

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My board passes the Zynq DRAM test application indicating that the DDR is correctly set up and is functionaly.

Still no further with the configuration issue.

 

 

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Contributor
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Registered: ‎02-24-2014

Re: Zynq 7z030 FSBL won't configure PL

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After various investigations, this turned out to be a HW DDR issue after all.

Even thought the Xilinx DRAM tests passed, by default they run with data caching enabled. This was masking DDR access problems. Once we turned off caching in the test tool menu, real errors were observed.

 

Following a fix to the DDR interface, PL configuration from flash worked straight away.

 

 

Chris

 

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Newbie
Newbie
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Registered: ‎11-05-2017

Re: Zynq 7z030 FSBL won't configure PL

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i am sorry to trouble you,but i don't konw howto turned off caching in the test tool menu,could you reply me as soon as possible.

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Registered: ‎01-22-2019

Re: Zynq 7z030 FSBL won't configure PL

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I have this problem with my target open in Vivado via JTAG. It bricks the FPGA bitsteram transfer. Simply closing the server solves the problem for me, there is nothing wrong with the boot per se.

vivado_hw_man.png