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Visitor chadgentry
Visitor
6,761 Views
Registered: ‎06-09-2014

Zynq AXI DMA Alignment Problem

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I've done a few example DMA projects with my zc706 and had no problems, but I have encountered a weird issue when writing my own. I wrote a VHDL core that would simply increment a counter everytime word is transmitted, asserting TLAST on the 16th word. This means that the core has data ready to send the moment a DMA transactionbegins. On the C side, I slightly modified some example code to perform 4 DMA RX transaction. The code should display a sequential count from 0 to 0x3F on 4 lines.

 

On the first transaction, the first 4 words are missing, instead the remaining 12 words are shifted over, and the memory remains unwritten for the last 4 bytes (I wrote 0xCC in all memory to distinguish when something isn't written).


--- Entering main() ---
Waiting for RX
Data received: 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0xCC 0xCC 0xCC 0xCC
Waiting for RX
Data received: 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
Waiting for RX
Data received: 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F
Waiting for RX
Data received: 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
XAxiDma_SimplePollExample: Passed

--- Exiting main() ---

 

I also created a simple loopback fifo that works perfectly as long as I set up the DMA receive before the transmit. If I set up the transmit, wait for it to finish, and then do the receive, I get the same problem as seen above.

How can I get DMA receive to work when there is data available the moment the transaction begins?

Thanks,
Chad

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Visitor chadgentry
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11,180 Views
Registered: ‎06-09-2014

Re: Zynq AXI DMA Alignment Problem

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I figured it out.  When the FPGA is first programmed, for some reason the DMA asserts READY for a few clock cycles.  My core saw this and began a transaction.  Then the alignment was permanently off.  The unfilled values were from LAST being asserted too early.  None of the other transactions were off because technically, the first 4 words were from the previous transaction.

 

I modified my core so that you had to enable it before it would try to respond to READY and it worked.

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Visitor chadgentry
Visitor
11,181 Views
Registered: ‎06-09-2014

Re: Zynq AXI DMA Alignment Problem

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I figured it out.  When the FPGA is first programmed, for some reason the DMA asserts READY for a few clock cycles.  My core saw this and began a transaction.  Then the alignment was permanently off.  The unfilled values were from LAST being asserted too early.  None of the other transactions were off because technically, the first 4 words were from the previous transaction.

 

I modified my core so that you had to enable it before it would try to respond to READY and it worked.

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Observer paul_paul
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6,368 Views
Registered: ‎09-06-2013

Re: Zynq AXI DMA Alignment Problem

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Hi! Here is similar problem:

AXI DataMover (S2MM) receives 4 beats of stream data just after its reset without any command

And the resason explanation and solution are given.

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