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Registered: ‎05-27-2013

Zynq AXI problem “S_AXI_RREADY”

Hello,

 

I have a problem with the AXI communication. To test the functionality of the AXI communication between Zynq PS and Zynq PL I implemented a Slave created with “Create and Package IP” (Vivado 2013.3).

 

The functionality of the design is: I Implemented a periodical Interrupt. When the Interrupt occurs, the ARM reads the data of the Slave (Switch postion “Xil_in32”) and writes these data to the Slave (LEDs flash “Xil_out32”).

 

When I start these function several times I got different results. In some cases it all works fine and the switch position can be read on the LEDs. In other cases the ARM stops by executing the Xil_In32 function.

 

To analyze the problem I set one PIN of the board HIGH when “S_AXI_RREADY” is HIGH. In the case the arm stops in the Xil_in32 function the control PIN is still LOW, so “S_AXI_RREADY” seems not to be HIGH. In the case the Xil_in32 function works and the LEDs flash the PIN is HIGH so “S_AXI_RREADY” should be HIGH for at least one Clock cycle.

I experimented with the response signals and at least I set all to a defined Value:

    S_AXI_RVALID <= '1';

    S_AXI_ARREADY <= '1';

    S_AXI_RID <= S_AXI_ARID;

    S_AXI_RLAST <= '1';

    S_AXI_RRESP <= "00";

 

But the problem is still the same, sometimes the Xil_in32 function works, and sometimes ARM stops and slave got no “S_AXI_RREADY” HIGH impuls.

 

Does anyone have the same problem or an advice?

 

Kind regards,

 

Michael

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2,192 Views
Registered: ‎05-27-2013

Re: Zynq AXI problem “S_AXI_RREADY”

Hello,

 

if I read the AXI documentation, I thought that the AXI comunnication in "create an package IP" example could be made easier. Seems that I was wrong, when I take the example communicaion It works fine.

 

Kind regards,

 

Michael

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