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Visitor goldscott
Registered: ‎10-22-2014

Zynq Ethernet Receive DMA bug

Hi All,


We’re using the Gigabit Ethernet Controller with our NetX networking stack to send data to a host over TCP. Occasionally the EMAC receive hardware presents us with a malformed packet from the host. Example: we are receiving an ACK packet with correct Ethernet and IP headers, but stale TCP header – it seems like the DMA only fills up to the first 26-42 bytes of the packet (i.e. everything before and including the IP header checksum is correct), the IP source and destination addresses stay constant in this use case, and the beginning of the TCP header (up to and including the SEQ number) also stay constant in this use case, so I can’t tell where exactly the DMA stops the transfer. I can tell the TCP header is stale because the ACK number and checksum are old – they’re the ACK & checksum of the packet that was previously received in that memory area.


The ACK packet comes in correctly on the wire (verified by a Wireshark trace). At first I was thinking it was a cache invalidation issue, but I’m using the debugger (Xilinx Platform Cable) to look in memory and I can see the new IP header and stale TCP header, so I’m led to believe that it’s a DMA issue.

The packets are in 32-byte aligned cache memory, so it’s not an alignment issue.

The buffer descriptor for the malformed packet looks normal and no errors are reported by the EMAC.


Some further info after writing the above:

The receive DMA doesn’t always write a complete packet from the EMAC FIFO to memory. Sometimes it will only write the first X bytes to memory, sometimes it will only write the last X bytes to memory. This is why sometimes we are seeing a new IP header with an old TCP header, and sometimes an old IP header with new TCP header.


Any ideas what's going on here?



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