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Observer f1xd
Observer
8,793 Views
Registered: ‎03-18-2013

Zynq, FSBL handoff interrupted on PS-PL level shifters turned on

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Hi!

I have a custom Zynq board. Test bitstream (works fine on PL), test app, no problems until i try to boot device from QSPI. FSBL works as it has to until handoff, then it calls ps7_post_config() which turns PS-PL level shifters. After that some interrupt occurs and FSBL IRQ handler initiates fallback.

There is no PL-PS activity expected with "hello world" in PS and simple LED blinker in PL. Both PL and PS seems to work fine. What could cause post-boot interrupt after turning on level shifters?

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Xilinx Employee
Xilinx Employee
16,150 Views
Registered: ‎02-01-2008

Re: Zynq, FSBL handoff interrupted on PS-PL level shifters turned on

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The problem is that the ps is not instantiated in the pl so as soon as the pl to ps levelshifters turn on, the ps will receive core_xxx interrupts forever. There is a define statement that you can set in the fsbl to prwvent enabling of the levelshifters. I dont recall the define but it will be something like NO_PS_IN_BITFILE

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Xilinx Employee
Xilinx Employee
16,151 Views
Registered: ‎02-01-2008

Re: Zynq, FSBL handoff interrupted on PS-PL level shifters turned on

Jump to solution
The problem is that the ps is not instantiated in the pl so as soon as the pl to ps levelshifters turn on, the ps will receive core_xxx interrupts forever. There is a define statement that you can set in the fsbl to prwvent enabling of the levelshifters. I dont recall the define but it will be something like NO_PS_IN_BITFILE

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Observer f1xd
Observer
8,751 Views
Registered: ‎03-18-2013

Re: Zynq, FSBL handoff interrupted on PS-PL level shifters turned on

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NON_PS_INSTANTIATED_BITSTREAM
Thank you for the solution, could you please look on another question? http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Slow-QSPI-programming-rate/td-p/561180
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