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146 Views
Registered: ‎09-19-2018

Zynq HPM1 AXI master interface simulation error

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I'm using a Zynq Ultrascale+ in a design. In the Zynq MPSoC PS, I have the PS to PL MAXI port HPM1 enabled, and set to 128 bits. When I simulate 32 bit writes out of that port using the zynq_ultra_ps_e_vip_v1_0_3.write_data function like ".write_data(32'hB000_CFFC, 4, 32'hDEAD0000, resp);", only writes to addresses ending in 0x0 have data on the wdata output. I'm simulating in Questa Sim -64 10.7b and using Vivado 2018.2.  

For example: addresses 0x0000, 0x0010, 0x0020, etc work fine. The addresses in between, 0x0004, 0x0008, 0x000C, 0x0014, etc, do not. The wstrb lines are active and in the correct four bit positions for all of the addresses, but the data is all zeros. In hardware, it works fine.

Ironically, if I change the HPM1 output port to a 32 bit interface, it simulates fine, but has the exact same failure in actual hardware as described above. So in hardware, I set the port to 128 bit and I have a 128 bit to 32 bit data width converter attached to that port. And then it works fine.

Has anyone else seen this problem?

Thanks,

Dale

 

HPM1_failure.JPG
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Xilinx Employee
Xilinx Employee
100 Views
Registered: ‎10-30-2017

Re: Zynq HPM1 AXI master interface simulation error

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Hi @rileyatraytheon ,

the address 0x0000, 0x0010, 0x0020 etc are alinged address and you can directly write data using write_data function call. But for unaligned address like  0x0004, 0x0008, 0x000C, 0x0014 you need to use the write_burst_strb api. 

Please check this post:

 https://forums.xilinx.com/t5/AXI-Infrastructure/MPSoC-VIP-example-write-data-and-read-data-are-always-4-bursts/m-p/996992#M3479

Best Regards,
Srikanth
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Xilinx Employee
Xilinx Employee
101 Views
Registered: ‎10-30-2017

Re: Zynq HPM1 AXI master interface simulation error

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Hi @rileyatraytheon ,

the address 0x0000, 0x0010, 0x0020 etc are alinged address and you can directly write data using write_data function call. But for unaligned address like  0x0004, 0x0008, 0x000C, 0x0014 you need to use the write_burst_strb api. 

Please check this post:

 https://forums.xilinx.com/t5/AXI-Infrastructure/MPSoC-VIP-example-write-data-and-read-data-are-always-4-bursts/m-p/996992#M3479

Best Regards,
Srikanth
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.