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Explorer
Explorer
1,851 Views
Registered: ‎04-23-2013

Zynq Interrupt priority

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Hello,

 

I have a project w/ 3 hardware interrupts, which are working.

 

Referencing UG585, I am not sure if I understand the priority issues

 

With XScuGic_SetPriorityTriggerType:

Does higher "level" mean higher priority?

Or does lower "level" mean higher priority?

 

Will a higher priority interrupt interrupt a lower priority interrupt?

Is there any guard against re-entrance?

 

 

 

I want the IRQF2P interrupts to be higher priority.

I use:

 

// Enable the IRQ_F2P0
XScuGic_Enable(&IntcInstance, XPS_FPGA0_INT_ID);
// Set interrupt priority (instance, port=XPS_FPGA0_INT_ID, level=x08/8=1, trigger type=rising edge
XScuGic_SetPriorityTriggerType(&IntcInstance, XPS_FPGA0_INT_ID, 0x08, 3);

 

// Enable the IRQ_F2P1
XScuGic_Enable(&IntcInstance, XPS_FPGA1_INT_ID);
// Set interrupt priority (instance, port=XPS_FPGA1_INT_ID, level=x08/8=1, trigger type=rising edge

XScuGic_SetPriorityTriggerType(&IntcInstance, XPS_FPGA1_INT_ID, 0x08, 3);

 

// Enable the Private Timer interrupt
XScuGic_Enable(&IntcInstance, XPS_SCU_TMR_INT_ID);
// Set interrupt priority (instance, port=XPS_FPGA0_INT_ID, level=x10/8=2, trigger type=rising edge
XScuGic_SetPriorityTriggerType(&IntcInstance, XPS_SCU_TMR_INT_ID, 0x10, 3);

 

 

Thanks,

Emmett

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1 Solution

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Scholar ericv
Scholar
2,210 Views
Registered: ‎04-13-2015

Re: Zynq Interrupt priority

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@emmettbradford

 

Contrary to the ARM M3 / M4 NVIC, the ARM A9 interrupts are not re-entrant.

When an interrupt is handled, no other interrupt can interrupt that processing.

The interrupt priorities are only meaningful when multiple interrupts are pending to be responded.

Priority level 0 is the highest.

 

If you have some very critical interrupts, you may want to dig into setting the GIC to dispatch them to both cores.

With proper ISR handler coding it will provide you with capability to handle 2 interrupts at the same time.

This works if your application is SMP multi-core.

 

You can get a freeware bare-metal SMP framework from us at:

code-time.com

 

 

 

3 Replies
Scholar ericv
Scholar
2,211 Views
Registered: ‎04-13-2015

Re: Zynq Interrupt priority

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@emmettbradford

 

Contrary to the ARM M3 / M4 NVIC, the ARM A9 interrupts are not re-entrant.

When an interrupt is handled, no other interrupt can interrupt that processing.

The interrupt priorities are only meaningful when multiple interrupts are pending to be responded.

Priority level 0 is the highest.

 

If you have some very critical interrupts, you may want to dig into setting the GIC to dispatch them to both cores.

With proper ISR handler coding it will provide you with capability to handle 2 interrupts at the same time.

This works if your application is SMP multi-core.

 

You can get a freeware bare-metal SMP framework from us at:

code-time.com

 

 

 

Adventurer
Adventurer
327 Views
Registered: ‎09-28-2018

Re: Zynq Interrupt priority

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Hi @ericv , @emmettbradford 

Would you look at following AR? I might be incorrect about this, but I believe interrupts can be interrupted themselves. I still need to test this om my R5 processor to confirm.  

https://www.xilinx.com/support/answers/54128.html

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Scholar ericv
Scholar
319 Views
Registered: ‎04-13-2015

Re: Zynq Interrupt priority

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@deville 

Natively, the A9 and R5 interrupts are not re-entrant.  But code can be added in the interrupt handler of any non-reentrant interrupt system to make them re-entrant.  If you look into the ARM reference manuals, once an interrupt is taken the interrupts are disabled in the CPSR until the "exit from interrupt" instruction.