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Visitor faumic
Visitor
299 Views
Registered: ‎06-04-2018

Zynq MPSoC MIO disable Pullups in Hardware

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Hello,

during the bring-up of a board with a Zynq MPSoC (2EG) i noticed that the MIO-Pins have internal pullups enabled (Absolutely no software running yet). I was assuming this is not the case if PUDC is High - but obviously this is only valid for the PL-IOs.

- Is there any chance to disable the MIO pullups via hardware configuration?
- Where can i find the specification of these pullups (Typical resistance etc.)?

Regards
Michael

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Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎09-01-2014

Re: Zynq MPSoC MIO disable Pullups in Hardware

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MIO pullup setting is controlled by the registers and the reset value of registers are set to internal pull-up.
See Table 28-2: MIO Control Registers from ug1085 for MIO registers.
Some boot relative MIO pins state might be changed by bootRom during boot.
The user can control the MIO state from in FSBL, pus_init will change Pull up/down per your setting in PCW.

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1 Reply
Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎09-01-2014

Re: Zynq MPSoC MIO disable Pullups in Hardware

Jump to solution

MIO pullup setting is controlled by the registers and the reset value of registers are set to internal pull-up.
See Table 28-2: MIO Control Registers from ug1085 for MIO registers.
Some boot relative MIO pins state might be changed by bootRom during boot.
The user can control the MIO state from in FSBL, pus_init will change Pull up/down per your setting in PCW.

View solution in original post