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Explorer
Explorer
1,417 Views
Registered: ‎03-17-2011

Zynq MPSoC PL reset

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Hello,

 

I have a MIG in the PL which requires an input reset. I need to configure a PLL prior to release the MIG reset.

Can I use a pl_resetn1 pin from the PS to control that reset? Or it's better to use an internal AXI GPIO.

 

Thanks.

--Sebastien
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1 Solution

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Voyager
Voyager
1,669 Views
Registered: ‎03-28-2016

Re: Zynq MPSoC PL reset

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In that case, I would use the internal AXI GPIO.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com

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4 Replies
Voyager
Voyager
1,395 Views
Registered: ‎03-28-2016

Re: Zynq MPSoC PL reset

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I would recommend using a "Processor System Reset" module.  Drive the "ext_reset_in" input from the PS and attach the "locked" signal from the PLL to the "dcm_locked" input.  That way you know the PLL is good to go before the MIG is released from reset.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Explorer
Explorer
1,369 Views
Registered: ‎03-17-2011

Re: Zynq MPSoC PL reset

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My PLL is external and programmed using an I2C. So only the software knows whenever the frequency is ok.
--Sebastien
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Voyager
Voyager
1,670 Views
Registered: ‎03-28-2016

Re: Zynq MPSoC PL reset

Jump to solution

In that case, I would use the internal AXI GPIO.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com

View solution in original post

Explorer
Explorer
1,273 Views
Registered: ‎03-17-2011

Re: Zynq MPSoC PL reset

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Ok. thanks Ted.
--Sebastien
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