12-24-2014 04:03 AM
PS power sequence is given as INT-AUX-PLL together and then IO.
PL power sequence is given as INT-BRAM, AUX and IO.
In my design : INT for both PL and PS is 1V. AUX for PL and PS is 1.8V. PS PLL is 1.8V. Both PS and PL IOs are 3.3V.
So, my inital thought was to use same sequencer and same converters for both PS and PL but now i have doubts because PS requires 1V and 1.8V to be ramped together. I didn't see that tricky "together" word in my previous look at DC characteristics document.
What do you think ?Could using one power sequence ( either of PL or PS ) cause permanent damage in my device ?
12-24-2014 05:28 AM - edited 12-24-2014 05:39 AM
You can use common power supplies for same voltages of PS and PL sections provided without affecting power-up/down sequences recommendations as per data sheet. You should not combine power supplies which voilates the power-up/down sequence recommendations.
Complete details of PS and PL power sequence given in page-7 of http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf (For ZC7010/ZC7015/ Zc7020). In case of ZC7030/7045 refer page-9 of http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf
Also note that you need to place complete decoupling capacitors recommendations of both power supplies in case of using common power supply for PS & PL supply rail. Please refer the following AR http://www.xilinx.com/support/answers/57819.html for example recommendations (for VCCINT & VCCPINT etc) common supply recommendations.
12-24-2014 05:50 AM
Thanks Umamaha. PL and PS power sequences are different : PS requires 1V and 1V8 to be ramped together while PL requires 1V8 to be ramped AFTER 1V.
So, i guess i need independent power supplies ?
One more question : I read AR you posted. It mentions flexibility of independent power supplies for PL and PS. I don't understand this : PS needs to be powered-up first for any deployed product, right ? This is because PL could only be programmed by PS or by PL JTAG. As, we can't use PL JTAG in any deployed product, powering-up PL first would be quite useless. What am i missing ?
12-24-2014 06:17 AM
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR,
VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are
isolated to prevent damage (Please note that isolates power planes in PCB layout).
There is internal POR (Power on reset) is there. It release reset only after all power supplies are ready. So JTAg problems(What you mentioned) does not occur even if PS powered before or after PL power supplies.
12-24-2014 11:39 AM - edited 12-24-2014 11:39 AM
Understand that we test every device to the sequence in the data sheet.
We characterize for all possible sequences, up anfd down.
So, if you wish to take advantage that 100% of parts are tested to the recommendations, use them.
If you wish to use any sequence, as long as you avoid any of the sequences
specifically prohibited, it will likely work just fine.
(page 7 of datasheet)...concerning Vcco at 3.3V