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Visitor semiory
Visitor
3,494 Views
Registered: ‎08-12-2017

Zynq SPI Slave does not receive

Hi everyone,


I'm repeating the post because it was written as reply in the wrong category.


I have following issue with SPI Slave communication on Zybo board.

 

The SPI (SPI1, MISO = MIO11; MOSI = MIO10; CLK = MIO12; SC = MIO13) is configured with following code in SDK:

 

        int Status;
	XSpiPs_Config *SpiConfig;
	/*
	 * Initialize the SPI driver so that it's ready to use
	 */
	SpiConfig = XSpiPs_LookupConfig(SpiDeviceId);
	if (NULL == SpiConfig) {
		return XST_FAILURE;
	}

	Status = XSpiPs_CfgInitialize(&SpiInstance, SpiConfig,
					SpiConfig->BaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	/*
	 * The SPI device is a slave by default and the clock phase
	 * have to be set according to its master. In this example, CPOL is set
	 * to quiescent high and CPHA is set to 1.
	 */
	Status = XSpiPs_SetOptions((&SpiInstance), (XSPIPS_CR_CPHA_MASK) | (XSPIPS_CR_CPOL_MASK));
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Set the clock devider to minimal vlaue of 4
	 * according datasheet the maximal slave frequency shall be SPI Clock / (Clock Divider * 2) = 200 / 8 = 25 MHz
	 * which is the 25 Mbit
	 */
	Status = XSpiPs_SetClkPrescaler((&SpiInstance), XSPIPS_CLK_PRESCALE_4);
	/*
	 * Perform a self-test to check hardware build
	 */
	Status = XSpiPs_SelfTest(&SpiInstance);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Connect the Spi device to the interrupt subsystem such that
	 * interrupts can occur. This function is application specific
	 */
	Status = SpiPsSetupIntrSystem(&IntcInstance, &SpiInstance, SPI_INTR_ID);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

 

 

The sends the data correctly (it reacts on "chip select", and shifts all the bits in the right way with the comming "clock")

SPI_Transfer.png

 

but does not receive anything....

If the XSpiPs_PolledTransfer() used, the controller stays in

 

             /*
             * Wait for the transfer to finish by polling Tx fifo status.
             */
            CheckTransfer = (u32)0U;
            while (CheckTransfer == 0U){
            StatusReg = XSpiPs_ReadReg(
                            InstancePtr->Config.BaseAddress,
                                XSPIPS_SR_OFFSET);
                if ( (StatusReg & XSPIPS_IXR_MODF_MASK) != 0U) {
                    /*
                     * Clear the mode fail bit
                     */
                    XSpiPs_WriteReg(
                        InstancePtr->Config.BaseAddress,
                        XSPIPS_SR_OFFSET,
                        XSPIPS_IXR_MODF_MASK);
                    return (s32)XST_SEND_ERROR;
                }
                CheckTransfer = (StatusReg &
                            XSPIPS_IXR_TXOW_MASK);
            }

 

 

forever because the StatusReg  is stays "0".

 

Could someone give an advice where the error can be? Did I forgot to configure something?

 

Thanks in Advance!

 

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11 Replies
Voyager
Voyager
3,473 Views
Registered: ‎06-24-2013

Re: Zynq SPI Slave does not receive

Hey @semiory,

 

Did you verify that there is something to receive, just to rule out hardware problems or detect issues with the MIO port config?

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Moderator
Moderator
3,465 Views
Registered: ‎07-31-2012

Re: Zynq SPI Slave does not receive

Hi,

 

Not sure if you are routing it through EMIO, if yes

 

You might not require all the signals under EMIO SPI_0 or SPI_1 when you route through EMIO. 

You mostly require below mentioned signals

  1. emio_spi0_m_o -> MOSI
  2. emio_spi0_m_i  -> MISO
  3. emio_spi0_sclk_o -> CLK
  4. emio_spi0_ss_o_n -> SS

You need to expand the SPI0 or SPI1 port in pcw and make below mentioned four signals as external pins by right click and “make external” one by one .

 

Regards

Praveen


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Visitor semiory
Visitor
3,443 Views
Registered: ‎08-12-2017

Re: Zynq SPI Slave does not receive

Hi @hpoetzl,

I did verify that the SPI Master (in my case a radio SOC CC2650) sends an array with 0x00 and 0xFF in the alternating manner to the Slave. But slave remains in the state of reception forerver...

 

I have already checked this issue using two Zybo-boards and the behavior is the same. Seems to be more general issue...

 

Thanks for your help.

 

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Visitor semiory
Visitor
3,442 Views
Registered: ‎08-12-2017

Re: Zynq SPI Slave does not receive

Thank for your quick reply,

I'm not using the EMIO, but MIO instead. I have attached a printscreen with part of configuration.MIO_Config.pngThanks in advance! 

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Scholar ericv
Scholar
3,427 Views
Registered: ‎04-13-2015

Re: Zynq SPI Slave does not receive

Did you check if the IXR_TXOW bit is clear to 0 in the interrupt mask register?

If it is set (interrupt is disabled), the IXR-TXOW bit in the status register bit will always be 0.

 

Regards

 

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Visitor semiory
Visitor
3,418 Views
Registered: ‎08-12-2017

Re: Zynq SPI Slave does not receive

Hi @ericv

 

I have added the following code to check the registers:

	u32 TX_Watemark = XSpiPs_GetTXWatermark(&SpiInstance);
	xil_printf("TX Watemark : ");
	xil_printf("%d \n\r",TX_Watemark);
    u32 RX_Watemark = XSpiPs_GetRXWatermark(&SpiInstance);
	xil_printf("RX Watemark : ");
	xil_printf("%d \n\r",RX_Watemark);
	u32 Check = (XSpiPs_ReadReg(SpiInstance.Config.BaseAddress, XSPIPS_SR_OFFSET) & XSPIPS_IXR_RXNEMPTY_MASK);
	xil_printf("IXR_RXNEMPTY (Rx FIFO Empty) : ");
	xil_printf("%d \n\r",(Check == XSPIPS_IXR_RXNEMPTY_MASK));
	Check = (XSpiPs_ReadReg(SpiInstance.Config.BaseAddress, XSPIPS_SR_OFFSET) & XSPIPS_IXR_TXOW_MASK);
	xil_printf("IXR_TXOW (Tx FIFO Overwater) : ");
	xil_printf("%d \n\r",(Check == XSPIPS_IXR_TXOW_MASK));


The status received after 200ms after transaction try (this time using the XSpiPs_Transfer((&SpiInstance),SendBufPtr, RecvBufPtr, ByteCount))
TX Watemark : 1
RX Watemark : 1
IXR_RXNEMPTY (Rx FIFO Empty) : 1
IXR_TXOW (Tx FIFO Overwater) : 0Best Regards

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Scholar ericv
Scholar
3,412 Views
Registered: ‎04-13-2015

Re: Zynq SPI Slave does not receive

@semiory

 

could you dump the interrupt mask register?

That's the one I was referring to.

 

Regards

 

 

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Highlighted
Scholar ericv
Scholar
3,391 Views
Registered: ‎04-13-2015

Re: Zynq SPI Slave does not receive

@semiory

 

An easy way to read that register is with this:

 

on SPI #0 : *((volatile unsigned int *)0xE0006010)

on SPI #1 : *((volatile unsigned int *)0xE0007010)

 

Regards

 

 

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Visitor semiory
Visitor
3,374 Views
Registered: ‎08-12-2017

Re: Zynq SPI Slave does not receive

Hi @ericv

 

I have read the registers as You mentioned:

 

#define SPI_0_REG *((volatile unsigned int *)0xE0006010)
#define SPI_1_REG *((volatile unsigned int *)0xE0007010)
{
xil_printf("Actual Register SPI 0 is :");
u32 REG = SPI_0_REG;
xil_printf("%08x :", REG);
xil_printf("Actual Register SPI 1 is :");
REG = SPI_1_REG;
xil_printf("%08x :", REG);
}

The result is:

Actual Register SPI 0 is : 0x00000000 -> is not activated.

Actual Register SPI 1 is : 0x00000027 -> 0b 00000000 00000000 00000000 00100111

 

Thanks in advance

 

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Visitor semiory
Visitor
1,876 Views
Registered: ‎08-12-2017

Re: Zynq SPI Slave does not receive

Update
I haven't made the SPI self test before....
If I try to make it, the self test does not pass and returns an error because the "Interrupt Status" register has a wrong value after reset.

Reading of status register returns "0", but shall return XSPIPS_ISR_RESET_STATE==4 .

Regards
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Adventurer
Adventurer
1,623 Views
Registered: ‎07-10-2015

Re: Zynq SPI Slave does not receive

Has the problem solved yet? My SPI slave received all 0s.

 

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