UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
299 Views
Registered: ‎02-26-2019

Zynq SoC AXI Interconnect Architecture

Jump to solution

Hi,

Is it possible to connect a AXI slave IP, such as axi_gpio or a custom IP, to PS Master AXI GP ports directly without using an AXI Interconnect IP?

Thanks.

Mustafa

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar u4223374
Scholar
196 Views
Registered: ‎04-26-2015

Re: Zynq SoC AXI Interconnect Architecture

Jump to solution

It's been a while since I looked closely, but I think the Zynq's ports use AXI3 whereas the Xilinx IP always uses AXI4. The Interconnect is required to do the conversion. I assume that if you write your own AXI block, you could implement AXI3 on that and plug it in directly.

View solution in original post

3 Replies
223 Views
Registered: ‎02-26-2019

Re: Zynq SoC AXI Interconnect Architecture

Jump to solution

There is a way how to connect custom AXI HDL outside of IP Integrator to a Zynq AXI Interface (AR# 56609),

However my question is different. I do not want to use Xilinx AXI Interconnect IP inside the block design. I want to carry out the Zynq AXI ports ( GP or HP) to outside of block design and than use custom AXI interfaces to connect in HDL part of the design.

Is there anything not supporting or not proposed to this kind of implementation?

0 Kudos
Highlighted
Scholar u4223374
Scholar
197 Views
Registered: ‎04-26-2015

Re: Zynq SoC AXI Interconnect Architecture

Jump to solution

It's been a while since I looked closely, but I think the Zynq's ports use AXI3 whereas the Xilinx IP always uses AXI4. The Interconnect is required to do the conversion. I assume that if you write your own AXI block, you could implement AXI3 on that and plug it in directly.

View solution in original post

133 Views
Registered: ‎02-26-2019

Re: Zynq SoC AXI Interconnect Architecture

Jump to solution

Thanks for the reply. So the main purpose of AXI interconnect block is to do AXI3 to AXI4 conversion. I think it also provides necessary synchronization and switch matrix stages if multiple master and slave ports are used however i am thinking to develop an outside HDL interconnect module which is not too much complex. Other issue is to add this port to memory adress space editor of block design. If i dont use an AXI interconnect block IP, it does not automatically add this interface to address editor. I think there must be simple solutions for manual editing the address editor for this external port.

Mustafa

 

 

 

0 Kudos