11-19-2019 01:49 PM
I have a simple Zynq US+ design that connects the PS M_AXI_HPM0_FPD port to block RAM through AXI interconnect and BRAM controller blocks (see pic). The HPM0 width is set to 32 bits and a data width of 32 bits is used for all other AXI ports in the path. The software engineer has coded a simple loop that writes to incremental addresses in the block RAM and reads/checks the result. What we see is that within each set of 4 32-bit addresses the first location is written but the next 3 are not. When viewing the bus with an ILA and doing 32-bit writes we see that the first write to 0xA000_0000 looks fine but the next write to 0xA000_0004 has WSTRB=0. It seems like the PS is treating the interface as 128-bit instead of 32-bit. We see the same thing regardless of whether the pointer to the RAM is set as u8* or u32* (in u8* mode the first four writes work, with WSTRB=1/2/4/8).
Is there any issue with accessing the PL this way (i.e. should we be calling a library function, doing some initial config, etc)? This smells like something that has a very simple explanation but I am just not seeing it.
Thanks - Jason
12-03-2019 12:49 PM - edited 12-03-2019 12:50 PM
Hi @jt94096 ,
I agree, this seems like something is a little goofy in the code.
Have you tried using the Xil_Out32()/Xil_In32() functions to write and read to the BRAM addresses?
Can you post your code and/or traces as well?
Early versions of the ZUS+ tools did not configure the bit widths of the PS-PL interfaces correctly (2016 time frame). I haven't seen a hardware configuration problem in a few years. Please refer to this AR for details: