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Visitor jblank
Visitor
624 Views
Registered: ‎02-06-2019

Zynq UltraScale+ SPI MIO to EMIO Routing

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Hello Everyone,

I am currently looking at the TRM for the Zynq UltraScale+ FPGA family and I am having a hard time determining what pins the PL-routed SPI signals can be used on.

 

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

 

Page 633 in the manual that can be accessed above deonotes the signals that can be accessed through the EMIO from the MIO for SPI. My question is, what PL pins are then capable of utilzing these SPI signals? Are there a specific set of pins that need to be used or can any of the single or differential pins be used? Also, page 766 in the manual states that there are 96 GPIO pins that are routed through the EMIO interface to the PL. Later on, however, at the bottom of page 767 it states these GPIO pins are not connected to the MIO interface in any way shape-or-form. 

 

TLDR: Does it matter what PL pins I use for the connection of SPI that has been passed through EMIO?

 

Thank you for your assistance.

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Xilinx Employee
Xilinx Employee
574 Views
Registered: ‎09-01-2014

Re: Zynq UltraScale+ SPI MIO to EMIO Routing

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You can use any FGPA I/O pin for EMIO SPI.
differential io is nothing but 2 input pins (p & n)
inside FPGA diffrential buffer will take these two input signal and convert to one signal line.
1 Reply
Xilinx Employee
Xilinx Employee
575 Views
Registered: ‎09-01-2014

Re: Zynq UltraScale+ SPI MIO to EMIO Routing

Jump to solution
You can use any FGPA I/O pin for EMIO SPI.
differential io is nothing but 2 input pins (p & n)
inside FPGA diffrential buffer will take these two input signal and convert to one signal line.