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Registered: ‎01-21-2018

Zynq UltraScale+ baremetal smp

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Hello,

I'm developping a baremetal smp application on the zcu102 board, is there some documentation and/or sample code about baremetal smp on this board?

Thanks

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Scholar
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Registered: ‎04-13-2015

Re: Zynq UltraScale+ baremetal smp

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@rfeneon

 

The way to get all A53 cores up and running is alike all ARM multi-core.

1 - reset all non #0 core

2 - set the VBAR for all non #0 cores

3 - release all non #0 cores from reset

 

The TRM doesn't say much, but the register description kind of gives all the info.

This is how we do it for the UltraScale+ (this code is running for core #0 only):

 

    MOV64    x1, _vector_table
    MOV64    x2, 0xFD5C0040                    // Base address of the RVBAR registers
    str      x1, [x2]                          // Put _vector_table in my RVBAR

    MOV64    x3, 0xFD1A0104                    // RST_FPD_APU register base address
    ldr      w4, [x3]
    orr      w4, w4, #(7 << 1)                 // Hold cores #1, #2 & #3 in reset
    str      w4, [x3]
    bic      w4, w4, #(7 << 11)                // Remove the power-on reset on cores #1 #2 & #3
    str      w4, [x3]

    str      x1, [x2, #8]                      // Set-up RVBAR for core #1
    str      x1, [x2, #16]                     // Set-up RVBAR for core #2
    str      x1, [x2, #24]                     // Set-up RVBAR for core #3
                                        
                                               // Release reset

    bic      w4, w4, #((1 << (OS_N_CORE))-2)   // -2 instead of -1 to not reset core #0
    str      w4, [x3]                          // Only OS_N_CORE are left running

 

After that , all cores are running starting from the same vector table reset entry.

 

If your RTOS can live without being in full control of the start-up, you can download our A53 "bare-metal" SMP freeware at

www.code-time.com

It has a few extra things alike full cache / MMU control (down to 4K pages), easy ISR handling, etc packaged with it.

 

Regards

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Scholar
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Registered: ‎03-22-2016

Re: Zynq UltraScale+ baremetal smp

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@rfeneon What you mean baremetal SMP? Interprocess communication mechanisms or how to run ELFs on several cores?

Usually the official response is to use OpenAMP

http://www.wiki.xilinx.com/OpenAMP

 

However as in standalone/baremetal all cores have equal access to memory, it is easy enough to coordinate areas of memory to share data. 

A SPSC (single producer, single consumer) is enough to take care of messaging - and it is very fast. 

You could use something like this:

http://www.vitorian.com/x1/archives/370

However in standalone you cannot have dynamic allocation so you got to pre-allocate that memory instead of using AllocT.

Here is some additional material:

 

Running two baremetal apps on the Zybo - this is exactly what you would do for the ZCU102. Only that it has 4 cores instead of 2. 

http://www.vitorian.com/x1/archives/587

 

Here is a minimal ZCU102 project - to complement the previous video

http://www.vitorian.com/x1/archives/599

 

This is a bit different - running baremetal & FreeRTOS with Microblaze on the ZCU102 without Zynq (reserved for other tasks). 

http://www.vitorian.com/x1/archives/575

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Re: Zynq UltraScale+ baremetal smp

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To be more precise, I have to port a RTOS (not FreeRTOS) with SMP support to the zcu102. I'm looking for information about the bootstrap process, in particular how to start the cores 1-3 from the core 0. Generally we have to write the address of the entry point function at some location then use the SEV instruction to wake up the other cores, but I didn't find any information about that in the Technical Reference Manual (UG1085).

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Re: Zynq UltraScale+ baremetal smp

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@rfeneon Does this help?

Zynq-7000 AP SoC Boot - Multiboot Tech Tip

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Multiboot+Tech+Tip

 

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Re: Zynq UltraScale+ baremetal smp

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No, the Zynq-7000 is different. I've found some information about smp on the Zynq-7000, but not for the Ultrascale... Thanks
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Re: Zynq UltraScale+ baremetal smp

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@rfeneon  I have two boards - one MPSoC (ZCU102) and one SOC Zynq7000 (ZC706) and they behave exactly the same w.r.t. the tools.

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Re: Zynq UltraScale+ baremetal smp

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@rfeneon

 

The way to get all A53 cores up and running is alike all ARM multi-core.

1 - reset all non #0 core

2 - set the VBAR for all non #0 cores

3 - release all non #0 cores from reset

 

The TRM doesn't say much, but the register description kind of gives all the info.

This is how we do it for the UltraScale+ (this code is running for core #0 only):

 

    MOV64    x1, _vector_table
    MOV64    x2, 0xFD5C0040                    // Base address of the RVBAR registers
    str      x1, [x2]                          // Put _vector_table in my RVBAR

    MOV64    x3, 0xFD1A0104                    // RST_FPD_APU register base address
    ldr      w4, [x3]
    orr      w4, w4, #(7 << 1)                 // Hold cores #1, #2 & #3 in reset
    str      w4, [x3]
    bic      w4, w4, #(7 << 11)                // Remove the power-on reset on cores #1 #2 & #3
    str      w4, [x3]

    str      x1, [x2, #8]                      // Set-up RVBAR for core #1
    str      x1, [x2, #16]                     // Set-up RVBAR for core #2
    str      x1, [x2, #24]                     // Set-up RVBAR for core #3
                                        
                                               // Release reset

    bic      w4, w4, #((1 << (OS_N_CORE))-2)   // -2 instead of -1 to not reset core #0
    str      w4, [x3]                          // Only OS_N_CORE are left running

 

After that , all cores are running starting from the same vector table reset entry.

 

If your RTOS can live without being in full control of the start-up, you can download our A53 "bare-metal" SMP freeware at

www.code-time.com

It has a few extra things alike full cache / MMU control (down to 4K pages), easy ISR handling, etc packaged with it.

 

Regards

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Re: Zynq UltraScale+ baremetal smp

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@ericv,

This is all the information I was missing, I think I can make some progress now. Many thanks!

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Re: Zynq UltraScale+ baremetal smp

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@rfeneon

You can find all the reference code for Xilinx embedded on Github:

https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa53/64bit/gcc/boot.S

 

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